User manual

17
Table 17. The Signal Highlighted in blue is the Signal Used to Clock TXCLK_IN_4
PIN# CNM NAME
J13 3Q0
K13 3Q1
H11 3Q_DS3
F10 3Q_DS2
F11 3Q_DS1
G11 3Q_DS0
H12 3Q_PS1
TXCLK_IN_4
J11 3Q_PS0
Table 18. The Signal Highlighted in blue is the Signal Used to Clock HOST_CLK and the purple Highlighted Signal is
Used to Clock the V2
PIN# CNM NAME
D13 4Q0
E13 4Q1
E11 4Q_DS3
C12 4Q_DS2
D11 4Q_DS1
F12 4Q_DS0
L12 4Q_PS1
HOST_CLK and
V2_CLK
J10 4Q_PS0
Table 19. The feedback signals connects to the internal Phase- Frequency Detector
PIN# CNM NAME
H3 FB_DS3
J2 FB_DS2
K2 FB_DS1
L2 FB_DS0
K4 FB_PS2
K3 FB_PS1
FEEDBACK
J4 FB_PS0
Tables 14-19 show the CMN banks that must be considered when using the CMN software to configure the desired
clocking of the 4-Port router. An example of how to determine the configuration settings of the CMN is provided
below.
5.2.9.5 CMN Configuration Example
Assume the user wanted to provide 200MHz clock to the TXCLK_IN_1, 16MHz clock to the
HADS3 Board, 16MHz clock to the HADS3 Board, and 12MHz to the HADS4 board. Given that
the Clock Network Manager II oscillator runs at 16MHz, the LCB FPGA will run at 16MHz, and
the LEON3FT can run at 16 or 32MHz.
Using the UTR2XLR816 Clock Network Manager II Frequency and Skew Calculator a schematic
detailing the output bank configuration requirements will be given. The output from the Frequency
and Skew Calculator will be used to configure the Clock Network Manager II register at location
0x00002000 to 0x00002018.
UTR2XLR816 Clock Network Manager II Frequency and Skew Calculator use the input the Input Frequency
Ref to 50MHz. There is a 50MHz oscillator that is used as the clock input reference.