User manual

5.2.9.4 Clock Network Manager Configuration

Each of the Divide Select banks contain output division selector and controller pins. There are four

ternary inputs used to control the 0Q[1:0], 1Q[1:0], 2Q[1:0], 3Q[1:0], 5Q[1:0], 7Q[1:0], and

FB_DS[1:0] output clock dividers, inverters, and enable controls. See Table 1 in the

UT7R2XLR816 Clock Network Manager Datasheet for output behavior resulting from each

combination of these pins.

The #Q_PS# pins are the bank output phase selectors. Depending on required skew these bits will

need to be set. These two ternary inputs are used to control the 0Q[1:0], 1Q[1:0], 2Q[1:0], 3Q[1:0],

5Q[1:0], 7Q[1:0], and FB_DS[1:0] output phase alignment. See Table 2 in the UT7R2XLR816

CNM Datasheet for output behavior output phase selections resulting from each combination of

these pins.

Table 14. The Signal Highlighted in blue is the Signal Used to Clock TXCLK_IN_1

PIN# CNM NAME

N4 0Q0

N3 0Q1

M6 0Q_DS3

M5 0Q_DS2

L5 0Q_DS1

M4 0Q_DS0

M2 0Q_PS1

TXCLK_IN_1

L3 0Q_PS0

Table 15. The Signal Highlighted in blue is the Signal Used to Clock TXCLK_IN_2

PIN# CNM NAME

N8 1Q0

N7 1Q1

K6 1Q_DS3

L7 1Q_DS2

K8 1Q_DS1

L8 1Q_DS0

L6 1Q_PS1

TXCLK_IN_2

K5 1Q_PS0

Table 16. The Signal Highlighted in blue is the Signal Used to Clock TXCLK_IN_3

PIN# CNM NAME

N12 2Q0

N11 2Q1

K10 2Q_DS3

L10 2Q_DS2

L11 2Q_DS1

M10 2Q_DS0

M9 2Q_PS1

TXCLK_IN_3

L9 2Q_PS0