User manual

15
UT200SpW4RTR
4-Port Router
UT54LVDS031LV
UT54LVDS031LV
T
X
_
D
I
V
0
T
X
_
D
I
V
4
Figure 5. TX_DIV[4:0] Jumper Locations
5.2.9.3.2 V2 Control
The Initialization Divide Registers can also be controlled using the on board Virtex-2
device. Control of the TX_DIV[4:0] pins can be achieved by writing code for the V2
device that address the signals listed in the following table.
Table 13. UT200SpW4RTR TX_DIV[4:0] to V2 Connection Table
Virtex 2 - XC2V500 (FG256/FGG256) UT200WSpW4RTR - 255 LGA
Signal Description Pin Signal Name Pin
IO_L91P_6 K4 TX_DIV4 H3
IO_L91N_6 K3 TX_DIV3 J3
IO_L93P_6 K2 TX_DIV2 K2
IO_L93N_6/VREF_6 K1 TX_DIV1 L2
IO_L94P_6 J4 TX_DIV0 M2