User manual

5.2.9.3 Initialization Divide Registers

All SpaceWire ports follow the initialization procedure as defined in

ECSS-E-ST-50-12C. Following are the key components of the initialization process. After a reset or

disconnect the link initiates operation at a signaling rate of 10 Mbps, ±1 Mbps. This provides the

system with a common data rate while the system is checked for proper operation. Once the

operation of the system is validated each of the four ports switches to the specified transmit data

rate. Each of the four ports must be capable of running at 10 ± 1 Mbps.

The initialization divide registers will all be loaded with the jumper settings value that pins

TX_DIV[4:0] on the UT200SpW4RTR are set to. These pins must be set to the proper settings in

order for the router to initialize at 10Mbps ± 1Mbps as defined in the SpaceWire Standard. The user

can use connector 73 or choose to use the V2 FPGA to configure the initialization divide registers.

If the user wishes to configure the router through port 3 and the transmit speed will be 100Mbps, the

user will need to set TX_DIV to 0x0A or 10 in decimal. Port 3 has the correct divider for the

10Mbps clock and can initialize the SpaceWire link. If the other ports are transmitting at different

data rates, the 10Mbps initialization data rate will not be correct. The user will then use Port 3 to set

the Transmit 10Mbps Register to the initialization data rate of 10Mbps. Once the router had

initialized and is in the run state, it will begin running at the specified TXCLK_IN rate.

NOTE: if TX_CLK is set to less than 10Mbps the Initialization Divide Register must be set to

0x01. The 4-Port Router will be able to initialize at these data rates. The user needs to be aware;

however, to be careful not to send any data until the links are in the run state. If the initialization

data rates are different, one side of the link could reach the run state before the other and, if that link

begins to send data, there is a good possibility the other side will disconnect because it received a

normal character before reaching the run state.

5.2.9.3.1 Manual Jumper Control (J73 header)

Configuration of the initialization divide registers can be accomplished using the

corresponding pin on the 5 pin J73 connector. The row of pins closest to the LVCMOS

SpW ports on the UT200SpW4RTR connected to 3.3V. The pins towards the LVDS SpW

ports are connected to VSS and the center row is connected to the initialization divide pin

as shown in the following table.

Table 12. J73 Initialization Divide Register pin assignments

UT200SpW4RTR – 255 LGA J73 Header

Signal Name Pin Pin

TX_DIV[0] M2 1

TX_DIV[1] L2 2

TX_DIV[2] K2 3

TX_DIV[3] J3 4

TX_DIV[4] H3 5