User manual

13
5.2.9.2 V2 Control
The CNN device can also be controlled using the on board Virtex-2 device. Control of the CNM
can be achieved by writing code for the V2 device that address the signals listed in the following
table.
Table 11. UT7R2XLR816 CMN to V2 connection table
Virtex 2 - XC2V500 (FG256/FGG256) UT7R2XLR816 - 168 LGA
Signal Description Pin Signal Name Pin
IO_L96N_1/GCLK3P A9 4Q_PS0 J10
IO_L05N_4/VRP_4 N11 4Q_PS1 L12
IO_L95P_0/GCLK6S C8 4Q_DS0 F12
IO_L95N_0/GCLK7P D8 4Q_DS1 D11
IO_L96P_0/GCLK4S A8 4Q_DS2 C12
IO_L96N_0/GCLK5P B8 4Q_DS3 E11
IO_L94P_4 T10 3Q_PS0 J11
IO_L94N_4/VREF_4 R10 3Q_PS1 H12
IO_L95P_4/GCLK2P P9 3Q_DS0 G11
IO_L95N_4/GCLK3S N9 3Q_DS1 F11
IO_L96P_4/GCLK0P T9 3Q_DS2 F10
IO_L96N_4/GCLK1S R9 3Q_DS3 H11
IO_L96P_1/GCLK2S B9 2Q_PS0 L9
IO_L95N_1/GCLK1P C9 2Q_PS1 M9
IO_L94N_1 A10 2Q_DS0 M10
IO_L94P_1/VREF_1 B10 2Q_DS1 L11
IO_L93N_1 C10 2Q_DS2 L10
IO_L93P_1 D10 2Q_DS3 K10
IO_L96P_2 H16 1Q_PS0 L3
IO_L96N_2 H15 1Q_PS1 M2
IO_L45N_2 F12 1Q_DS0 L8
IO_L45P_2/VREF_2 G12 1Q_DS1 K8
IO_L43N_2 F15 1Q_DS2 L7
IO_L43P_2 F16 1Q_DS3 K6
IO_L91P_4 T11 0Q_PS0 L3
IO_L91N_4/VREF_4 R11 0Q_PS1 M2
IO_L92P_4 M10 0Q_DS0 M4
IO_L92N_4 M11 0Q_DS1 L5
IO_L93P_4 P10 0Q_DS2 M5
IO_L93N_4 N10 0Q_DS3 M6
IO_L01N_4/BUSY/DOUT(1) T14 FB_PS0 J4
IO_L02P_4/D1 R13 FB_PS1 K3
IO_L03P_4/D3/ALT_VRN_4 P12 FB_PS2 K4
IO_L03N_4/D2/ALT_VRP_4 N12 FB_DS0 L2
IO_L04N_4/VREF_4 R12 FB_DS2 J2
IO_L04P_4 T12 FB_DS1 K2
IO_L05P_4/VRN_4 P11 FB_DS3 H3
IO_L91N_2 G13 FREQ_SEL K11
IO_L91P_2 G14 /CM_LV H10
IO_L93N_2 G15 /OE D9
IO_L93P_2/VREF_2 G16 TEST B2
IO_L94N_2 H13 REF_SEL F3
IO_L94P_2 H14 /RST_DIV F2