User manual

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Table 7. LVDS Receiver UT54LVDS032LV Enable Configuration
Enable Signal Input Output
EN /EN RIN+ - RIN- ROUT
L H X Z
VID≥0.1V H
VID≥-0.1V L
All other combinations
of ENABLE signals
Fail Safe Mode H
Table 8. Switch 2 LVDS Devices Connection Table
Switch 2 (SW2)
Position Name Port Enabled
1 TX 1 ENABLE (EN) 1 and 2
2 TX 1 ENABLEB (/EN) 1 and 2
3 RX 1 ENABLE (EN) 1 and 2
4 RX1 ENABLEB (/EN) 1 and 2
5 TX 2 ENABLE (EN) 3 and 4
6 TX 2 ENABLEB (/EN) 3 and 4
7 RX 2 ENABLE (EN) 3 and 4
8 RX 2 ENABLEB (/EN) 3 and 4
5.2.8 Time Code Interface
The UT200SpW4RTR time code interface is tied to the V2 FPGA. Time code signals can be monitored by writing a
user program that looks at these signals.
Table 9. Time code interface connection table
Virtex 2 - XC2V500 (FG256/FGG256) UT200WSpW4RTR - 255 LGA
Signal Description Pin Signal Name Pin
IO_L01N_2 C16 TIMECODE1 T3
IO_L01P_2 D16 TIMECODE0 T2
IO_L02N_2/VRP_2 D14 TIMECODE3 R2
IO_L02P_2/VRN_2 D15 TIMECODE2 T4
IO_L03N_2 E13 TIMECODE5 R4
IO_L03P_2/VREF_2 E14 TIMECODE4 R3
IO_L04N_2 E15 TIMECODE7 R6
IO_L04P_2 E16 TIMECODE6 R5
IO_L06N_2 F13 TICKOUT T7
IO_L06P_2 F14 TICKIN T6
5.2.9 Clock Interface
The Clock Network Manager (CNM) is used to provide the five clocks to the UT200SpW4RTR device. The clock
signals are HOST_CLK, TXCLK_IN_1, TXCLK_IN_2, TXCLK_IN_3, TXCLK_IN_4, and a clock to the V2 FPGA.
Please refer to the UT7R2XLR816 Clock Network Manager datasheet for further information.
The 43 pin headers on the board can be used for the configuration of the CNM. Each of the configuration signals are
3-level inputs. The middle row of headers is connected directly to the corresponding signal on the CNM device. The
surrounding rows of pins are connected to VDD = 3.3V and VSS = 0.0V.
The UT7R2XLR816 Clock Network Manager Software GUI should be downloaded from www.aeroflex.com/clocks
to assist in the proper configuration selection of the clocks that are provided to the SpaceWire router.