Standard Products UT200SpW4RTR-EVB 4-Port SpaceWire Router Evaluation Board Users Guide User Manual November, 2010 www.aeroflex.com/spacewire 1.0 INTRODUCTION The UT200SpW4RTR-EVB is a 4-Port SpaceWire Router evaluation board designed to allow the system designer access to all the features of the UT200SpW4RTR 4-Port router as defined in the datasheet (www.aeroflex.com/spacewire). The 4-Port router is capable of operating at data rates from 10 to 200 Mbps.
4.0 FUNCTIONAL DIAGRAM PAGE 2 Clock Network Manager II 4 LVCMOS Ports SpW PORT Powered from 3.3V Powered from 3.3V SpW PORT 2.5V Regulator 4 LVDS SpW UT200SpW4RTR SpaceWire Router HOST PORT 1.5V Linear Regulator SpW PORT SpW PORT SpW PORT 4 TX_CLK_IN HOST CLK LVDS UT54LVDS031LV UT54LVDS032LV Xilinx PROM Xilinx V2 JTAG PAGE 1 +3.3V +5.0V JTAG Gaisler Board J9 Connector PAGE 4 2.5V Power Plane 3.3V Power Plane 5.0V Power Plane PAGE 6 1.
5.0 FEATURES AND GENERAL OPERATION The Aeroflex 4-Port SpaceWire Router evaluation board is designed to provide the user a flexible means to configure, control, access, and route data through the UT200SpW4RTR device. Power to the board may be provided through the J9 connector on the GR-UT699 CPCI Development Board or through the BNC connectors. Only one power source should be used at a time. Clocking of the board is done via the UT7R2XLR816 Clock Network Manager.
5.1 Power 5.1.1 External Power Power to the UT200SpW4RTR-EVB may be provided externally using the three BNC connectors. 5.0V, 3.3V and 2.5V must be provided to the board. In order to use external power provided by the BNC connectors the user must jumper J57, J58, and J59. These jumpers ensure that external power is flowing to the board. Ensure that Jumpers J64 and J65 are removed! To avoid large surge currents in the UT200SpW4RTR device, VDD = 3.3V (J57) should be powered up either before VDDC = 2.
.1.2 Aeroflex Gaisler Board Power Power to the UT200SpW4RTR-EVB may also be provided from the J9 connector on the GR-CPCI-UT699 LEON3FT CPCI Development Board. Jumpers J64 and J65 must be set in order for the 120 pin J63 connector on the 4-Port EVB to receive power from the LEON-3FT board. J63, the 120 pin connector, is located on the back side of the UT200SpW4RTR-EVB. Use caution when mating the UT200SpW4RTR-EVB to the LEON-3FT evaluation board.
5.2 UT200SpW4RTR 4-Port Router The 4-Port router can be easily configured using any of the four SpaceWire ports or the Host port connected to the V2. If the user is going to use the XC18V04VQ44 Xilinx PROM (44-VTQFP) with the Virtex 2 - XC2V500 (FG256/FGG256) jumpers should be added to J6, J9, and J10 for proper access from the PROM to the FPGA. Jumpers J6, J9 and J10 are located in the center on the top of the board. 5.2.
5.2.4 /RST Control Signal The /RST pin is connected to push button switch SW1. /RST is active low. If the router needs to be reset the user can push this switch and the router resets. After the router is reset the user should ensure that all the configuration and status register are properly set to the desired configuration. 5.2.4.1 Manual Reset Control (SW1) Control of this pin can be accomplished using switch SW1. pushing SW1 will reset the router device.
5.2.5 HOST Port Interface Access to the 5th port of the HOST port of the UT200SpW4RTR can be accomplished by writing code targeted to the Virtex 2 FPGA. Signals used to access the HOST port are listed below. Access to the HOST port can only be achieved by using the V2. Be sure to jumper headers J6, J9, and J10 to ensure proper access from the PROM to the V2 FPGA. Table 1.
Table 3.
IO_L91N_3 IO_L93N_3/VREF_3 IO_L93P_5 IO_L93N_5 IO_L92P_5 IO_L92N_5 5.2.7 K14 K16 N7 P7 M6 M7 OEN (LEON-3FT) WRITEN (LEON-3FT) RAMOEN0 RAMOEN1 RAMSN0 RAMSN1 47 46 66 67 55 54 SpaceWire Interfaces 5.2.7.1 LVDS Interface The LVDS SpaceWire ports on the UT200SpW4RTR are connected to SpaceWire connectors located closest to the Router device. Table 4.
Table 7. LVDS Receiver UT54LVDS032LV Enable Configuration Enable Signal EN /EN L H All other combinations of ENABLE signals Input RIN+ - RINX VID≥0.1V VID≥-0.1V Fail Safe Mode Output ROUT Z H L H Table 8.
5.2.9.1 Manual Jumper Control (43 Pin header) Control of the CNM can be accomplished using the corresponding pin on the 43 pin connector to set the proper configuration as reported by the UT7R2XLR816 Clock Network Manager Software GUI. The row of pins on the left or on the inside of the board are connected to 3.3V. The pins towards the outside of the board are connected to VSS and the center row is connected to the pin of the CNM. The silkscreen on the board indicates which signal is routed to which pin.
5.2.9.2 V2 Control The CNN device can also be controlled using the on board Virtex-2 device. Control of the CNM can be achieved by writing code for the V2 device that address the signals listed in the following table. Table 11.
5.2.9.3 Initialization Divide Registers All SpaceWire ports follow the initialization procedure as defined in ECSS-E-ST-50-12C. Following are the key components of the initialization process. After a reset or disconnect the link initiates operation at a signaling rate of 10 Mbps, ±1 Mbps. This provides the system with a common data rate while the system is checked for proper operation. Once the operation of the system is validated each of the four ports switches to the specified transmit data rate.
0 UT54LVDS031LV TX _D IV V4 TX_DI UT200SpW4RTR 4-Port Router UT54LVDS031LV Figure 5. TX_DIV[4:0] Jumper Locations 5.2.9.3.2 V2 Control The Initialization Divide Registers can also be controlled using the on board Virtex-2 device. Control of the TX_DIV[4:0] pins can be achieved by writing code for the V2 device that address the signals listed in the following table. Table 13.
5.2.9.4 Clock Network Manager Configuration Each of the Divide Select banks contain output division selector and controller pins. There are four ternary inputs used to control the 0Q[1:0], 1Q[1:0], 2Q[1:0], 3Q[1:0], 5Q[1:0], 7Q[1:0], and FB_DS[1:0] output clock dividers, inverters, and enable controls. See Table 1 in the UT7R2XLR816 Clock Network Manager Datasheet for output behavior resulting from each combination of these pins. The #Q_PS# pins are the bank output phase selectors.
TXCLK_IN_4 Table 17. The Signal Highlighted in blue is the Signal Used to Clock TXCLK_IN_4 PIN# J13 K13 H11 F10 F11 G11 H12 J11 CNM NAME 3Q0 3Q1 3Q_DS3 3Q_DS2 3Q_DS1 3Q_DS0 3Q_PS1 3Q_PS0 HOST_CLK and V2_CLK Table 18. The Signal Highlighted in blue is the Signal Used to Clock HOST_CLK and the purple Highlighted Signal is Used to Clock the V2 PIN# D13 E13 E11 C12 D11 F12 L12 J10 CNM NAME 4Q0 4Q1 4Q_DS3 4Q_DS2 4Q_DS1 4Q_DS0 4Q_PS1 4Q_PS0 FEEDBACK Table 19.
Click [Configure] button Bank 0 Bank 1 Bank 2 Bank 3 Bank 4 Bank 5 Bank 6 Bank 7 200 200 100 100 50 (HOST_CLK must be set to 0.25 times the fastest TXCLK_IN) Don’t Care Don’t Care Don’t Care Click [Calculate Configuration] Select the configuration that best meets the systems needs. Click [Return Selected Configuration] Figure 6.
Figure 7. Configuration Schematic This is the configuration schematic that will be used to configure the Clock Network Manager for the clocking of the UT200SpW4RTR and the V2 FPGA.
Table 20.
UT54LVDS031LV UT200SpW4RTR 4-Port Router Figure 8.
5.2.9 Router Configuration Protocol The user may want to access to the configuration and status registers. Access to these registers can be accomplished though any one of the four SpaceWire ports or the External Port. The default configuration is for all ports to be configuration ports. If one or more ports are set up to be configuration ports, only one configuration command should be sent at a time. 5.2.9.
Figure 10. Configuration Read Command 5.2.9.9 Configuration Read Response A read response will be sent back to the requesting address after a Read command is executed. The Read packet command as shown in Figure 5 sets, up the address to read data from (Address LSB/MSB) and how many 8-bit values to read (Count), and the return address bytes path. After the Read command is executed a Read Response command will be issued and contains the data byte pairs read from the specified address.
• • • • • • • • • • Use Write configuration protocol into port 5 of the router Address Bytes: NONE Needed 0x00 for configuration Router ID: 00 for router (default) Protocol ID: 00 for no protocol used Packet Type: 00 is Write Set up Data Format o Address LSB: 02 LSB o Address MSB: 01 MSB of register location 0x0102 Write in Data o Data LSB: 10 Bit15 87 4 0 o Data MSB: 00 00000000 00010000 Checksum: 13 this is the sum of the final destination address, router ID, protocol ID, packet type, and the address and
6.0 PORT ADDRESSING 6.1 Path Addressing Path Addressing is defined as a series of one or more characters at the start of the packet that define the route, or path, that the packet should take across a SpaceWire network. The destination address is specified as a sequence of router output port numbers used to route the packet across the network. The drawback is that the destination address can become relatively large if several routing switches have to be traversed.
6.5.2 Group Adaptive Address Bits Bits [9:5] are used when Group Adaptive has been enabled and the port selected by the Primary Logical Address Bits is busy. If group adaptive routing is not enabled and port selected by the Primary Logical Address Bits is busy, the packet waits until the selected port is free. 6.5.3 Enable Header Delete Bit Bit [10] is used to enable the header delete function for the port selected by either the Group Adaptive Address bits or the Primary Logical Address Bits.
• • • • • • • Write directly into port 5 of the Router, no Address Bytes required 0x00 for configuration Router ID: 00 for router ID (default) Protocol ID: 00 for no protocol used Packet Type: 00 is Write Set up look-up table o Address LSB: 20 sets up first address in look up table o Address MSB: 00 the address MSB is always 00 because the address range of the Logical Addresses is 0x0020 to 0x00FF Write in Data o Data LSB: 01 sets up port 1 of Router (this will set up logic such that is register 0x0020 is
6.5.8 Look up table configuration Example 2 Assume the user wants to confirm the configuration write just preformed on look up table address 0x0020 was completed correctly. The user can then use the read configuration command. The following example details hope to accomplish this.
To quickly get the UT200SpW4RTR-EVB up and running the following steps should be followed 1. Connect headers J57, J59, and J58 a. This will enable external power supplies to be used b. Ensure that headers J64 and J65 are not connected. 2. Connect BNC connectors to J54 3.3V, J56 2.5V , and J55 5.0V 3. Determine which SpW interface you would like to use a. LVDS – Connect Pin 2 J70 to VDD b. LVCMOS – Connect Pin 2 J70 to VSS 4. Are you going to use the HOST port? a.
The UT200SpW4RTR-EVB can plug directly into the J9 connector on the LEON-3FT evaluation board. A ribbon cable can also be used to easily use the SpaceWire evaluation board with the LEON-3FT board when the LEON board is plugged into a cPCI chassis. Using the ribbon cable to connect the SpaceWire evaluation board to the LEON 3FT GR-UT699 evaluation board allows for easier access to the SpW ports on the UT200SpW4RTR-EVB board. The virtex-2 FPGA is connected to the HOST port of the UT200SpW4RTR device.
10.0 BOARD SCHEMATICS The schematics in Appendix A are for reference ONLY.
5 4 3 2 1 Change Block Redesigned board for customer use Board can plug into Aeroflex/Gaisler LEON-3FT Evaluation Board or be used as a table top board UT200SpW4RTR-CUSTOMER-EVB Schematic D D C C B B A NOTICE TO ALL PERSONS RECEIVING THIS DRAWING: THIS DOCUMENT IS PROPERTY OF AEROFLEX COLORADO SPRINGS AND IS DELEVERED ON THE EXPRESS CONDITION THAT IT IS NOT TO BE DISCLOSED, REPRODUCED IN WHOLE OR IN ANY PART, OR IS USED FOR MANUFACTURE FOR ANYONE OTHER THAN AEROFLEX WITHOUT ITS WRITTEN CONSENT;
5 4 C1 C2 C3 C4 C5 C6 0.1uF0.1uF0.1uF0.01uF 0.01uF 0.
5 4 3 2 1 VDD3_3V D R14 DNI C69 R13 DNI C51 C52 C53 C54 C55 DNI 0.01uF 0.1uF0.01uF 0.1uF 0.01uF 0.1uF0.01uF C56 C57 0.1uF + R8 VDD3_3V DNI DO NOT INSTALL Silkscreen TX_CLK4 R11 DNI R12 DO NOT INSTALL DNI Silkscreen TX_CLK3 C142 C50 DNI C145 47uF + R10 DNI DO NOT INSTALL Silkscreen TX_CLK2 C141 C146 47uF C58 C59 0.01uF C60 C61 C62 C63 C64 C65 C66 C67 0.1uF0.01uF 0.01uF 0.1uF 0.1uF 0.01uF 0.1uF 0.01uF 0.
1 N7 N8 33 1 D4 RadClock II - Clocks 6Q0 6Q1 5Q0 5Q1 3Q1 3Q0 2Q1 2Q0 LOCK LVD_INLVD_IN+ REF FB_OUT FB_IN XTAL_IN XTAL_OUT 1Q1 1Q0 N11 N12 7Q0 7Q1 UT7R2XLR816 K13 J13 TXCLK3 LOCK J13 HEADER 1 A3 A4 A7 A8 A11 A12 4Q1 4Q0 TXCLK3 0Q1 0Q0 D E13 D13 TXCLK2 PAGE2 Silkscreen 33 Silkscreen R28 R29 33 HOST_CLK 33 Silkscreen R27 33 TXCLK4 FB_PS0 FB_PS1 FB_PS2 FB_DS0 FB_DS1 FB_DS2 FB_DS3 CNM_LV_CM PAGE1 CNM_FREQ_SEL PAGE1 CNM_TEST PAGE1 CNM_OE PAGE1 RST_DIV PAGE1 REF_SEL PAGE1 U4C J32
5 4 3 C129 0.01uF C128 0.1uF 2 1 16 VDD3_3V EN 4 LVDSTX_EN1 EN Silkscreen TX1_D R32 1 TX1D Silkscreen 33 R33 TX1_S 7 TX1S Silkscreen 33 TX2_D R34 PAGE1,2 TX2D PAGE1,2 TX2S P5 8 5 9 4 8 3 7 2 6 1 9 Silkscreen 33 R35 TX2_S 15 33 DIN1 DOUT1+ DOUT1- DIN2 DOUT2+ DOUT2- DIN3 DOUT3+ DOUT3- DIN4 DOUT4+ DOUT4- 2 3 6 5 10 11 14 13 C131 PAGE1,2 RX1S PAGE1,2 RX1D PAGE1,2 RX2S Silkscreen RX1_S 8 0.
5 J55 BNC Silkscreen 5.0V POWER 1 2 2 1 2 Silkscreen 2.5V POWER VDD5_0V 1 2 1 VDD3_3V J56 BNC VDD2_5V 1 1 2 VDD3_3V 1 3 2 J54 BNC C72 + 2 Silkscreen 3.3V POWER 4 10uF J59 HEADER 2 J58 HEADER 2 U1J A1 A16 B2 B15 C3 C14 F6 F11 G7 G8 G9 G10 H10 H7 H8 H9 J7 J8 J9 J10 K7 K8 K9 K10 L6 L11 P3 P14 R2 R15 T1 T16 D VDD3_3V C87 + C86 + 33uF 33uF + 33uF + 33uF C91 33uF C85 + C84 + 33uF C136 33uF C83 + C82 VDD2_5V + 33uF C92 C93 0.01uF 0.
5 4 3 2 1 Change Block D D J63 PAGE1 RAMOEN0 PAGE1 RAMOEN1 PAGE1 GR_IOSN PAGE1 GR_READ A1 PAGE1 PAGE1 A3 PAGE1 A5 PAGE1 A7 C MEZ_33 J64 1 2 Silkscreen GR 5.0V POWER MEZ_5 PAGE1 PAGE1 PAGE1 PAGE1 PAGE1 PAGE1 PAGE1 PAGE1 A9 A11 A13 A15 A17 A19 A21 A23 PAGE1 PAGE1 PAGE1 PAGE1 PAGE1 PAGE1 PAGE1 PAGE1 A25 A27 D16 D24 D17 D25 D18 D26 PAGE1 PAGE1 PAGE1 PAGE1 PAGE1 PAGE1 PAGE1 PAGE1 HEADER 2 VDD5_0V PAGE1 PAGE1 B MEZ_5 J65 1 2 Silkscreen GR 3.
ORDERING INFORMATION UT200SpW4RTR-EVB: UT ***** Device Type: 200SpW4RTR-EVB = 4-port SpaceWire Evaluation Board 32
Aeroflex Colorado Springs - Datasheet Definition Advanced Datasheet - Product In Development Preliminary Datasheet - Shipping Prototype Datasheet - Shipping QML & Reduced Hi – Rel 33
