GR-UT699 Development Board User Manual AEROFLEX GAISLER AB Rev. 0.
GR-UT699 Development Board User Manual Information furnished by Aeroflex Gaisler AB is believed to be accurate and reliable. However, no responsibility is assumed by Aeroflex Gaisler AB for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Aeroflex Gaisler AB.
GR-UT699 Development Board User Manual TABLE OF CONTENTS 1 INTRODUCTION...........................................................................................................7 1.1 1.2 1.3 1.4 2 Overview...................................................................................................................... 7 References...................................................................................................................9 Handling...........................................
GR-UT699 Development Board User Manual LIST OF TABLES Table 3-1: Default Status of Jumpers/Switches..............................................................................27 Table 4-1: List of Connectors......................................................................................................... 32 Table 4-2: J1 UART-1 - Serial Interface (RS232) connections .....................................................34 Table 4-3: J2 RJ45-ETHERNET Connector.....................................
GR-UT699 Development Board User Manual LIST OF FIGURES Figure 1-1: GR-UT699 Development Board.....................................................................................8 Figure 2-1: Block Diagram of GR-UT699 board.............................................................................11 Figure 2-2: UT699 ASIC................................................................................................................. 12 Figure 2-3: On-Board Memory Configuration.........................
GR-UT699 Development Board User Manual Intentionally Blank © Aeroflex Gaisler AB March 2013, Rev. 0.
1 GR-UT699 Development Board User Manual INTRODUCTION 1.1 Overview This document describes the GR-UT699 Development Board. The purpose of this equipment is to provide developers with a convenient hardware platform for the evaluation and development of software for the Aeroflex UT699RH RadHard 32-bit Fault-Tolerant LEON 3FT/SPARCTM V8 Processor ASIC device. The UT699 is a Leon3FT based custom ASIC for Aerospace applications.
• • • • • • • • • GR-UT699 Development Board User Manual One Serial UART interface (RS232) Ethernet JTAG - DSU Two CAN bus interfaces Four Spacewire interfaces Serial DSU UART (Mini-AB USB connector) 16 pins General Purpose I/O Port Push Buttons for RESET and BREAK LED indicators To enable convenient connection to the interfaces, the connector types and pin-outs are compatible with the standard connector types for these types of interfaces.
GR-UT699 Development Board User Manual 1.3 Handling ATTENTION : OBSERVE PRECAUTIONS FOR HANDLING ELECTROSTATIC SENSITIVE DEVICES This unit contains sensitive electronic components which can be damaged by Electrostatic Discharges (ESD). When handling or installing the unit observe appropriate precautions and ESD safe practices. When not in use, store the unit in an electrostatic protective container or bag.
2 GR-UT699 Development Board User Manual ELECTRICAL DESIGN 2.1 Block Diagram The GR-UT699 board provides the electrical functions and interfaces as represented in the block diagram, Figure 2-1.
GR-UT699 Development Board User Manual Figure 2-2: UT699 ASIC 2.
GR-UT699 Development Board User Manual 2.3.1 SRAM The GR-UT699 board is laid out with two SRAM memory banks but only has one bank mounted as standard. Each bank is made up of five CY7C1069AV33. These devices are 16Mbit (2Mbyte x 8 bit devices with 10 or 12 ns access times. The five devices provide (32 + 8) bit wide SRAM memory paths allowing EDAC operation. These memory banks are mapped as RAMBANK0 and RAMBANK1.
CAN CAN TRANSCEIVER TRANSCEIVER TXD RXD CAN_L CAN_H CAN CAN TRANSCEIVER TRANSCEIVER CAN_L CAN interface 2 CONTROLLER LOGIC IN ASIC RXD CAN_H CAN interface 1 TXD GR-UT699 Development Board User Manual Figure 2-4: Block Diagram of the CAN interface 2.4.1 Configuration of Bus Termination The CAN interfaces on the board can be configured for either end node or stub-node operation by means of the jumpers JP3 and JP4 for interface 1 and 2 respectively, as shown in Figure 2-5.
GR-UT699 Development Board User Manual Figure 2-5: Transceiver and Termination Configuration (one of 2 interfaces shown) 2.4.2 Configuration of Slew Rate The SN65HVD230 transceiver device used on the board has the facility to set the device into STANDBY mode, by connecting an active high external signal to pin 8 of the device (refer to the device data sheet). However, on this board this is tied to permanently 'low' to enable the CAN bus Transceivers.
GR-UT699 Development Board User Manual The pin out and connector types for these Spacewire interfaces conform to the Spacewire standard, as shown in Figure 2-6. The inner shield pin (pin3 of the connector) is connected to DGND via a Zero-ohm resistor. 2.5.
GR-UT699 Development Board User Manual 2.6 Serial Interface The UT699RH ASIC, provides a single Serial port, with TXD/RXD pins, and the GR-UT699 board provides an RS232 driver/receiver chip and routes these signals to a front panel connector. The front panel connector type for the UART interface is Female D-Sub 9 pin type with a standard pin-out for serial links. SUB-D 9 pin Female TXD UT699RH ASIC RS232 DRIVER/ RECEIVERS RS232 INTERFACE RXD Figure 2-7: Serial interface 2.
GR-UT699 Development Board User Manual normal use the DSU feature will always be enabled to allow processor control and program debugging via the DSU link. An LED is provided on the PCB to indicate the conditions of the DSUACT signal from the UT699 processor. Additionally connections are provided to an LED indicator on the front panel of the Unit.
GR-UT699 Development Board User Manual 2.8 Oscillators and Clock Inputs The oscillator and clock scheme for the UT699 ASIC is shown in Figure 2-9. MEMORY MEMORYEXPANSION EXPANSION CONNECTOR CONNECTOR COAX CONNECTOR ZERO ZERO DELAY DELAY BUFFER BUFFER TBD TBDMHz MHz SYS CLK DIL8 SOCKET UT699RH ASIC COAX CONNECTOR SDCLK SDRAM SDRAM MODULE MODULE SPW CLK TBD TBDMHz MHz DIL8 SOCKET Ethernet Ethernet PHY PHY 25 25MHz MHz ETH_TXCLK ETH_RXCLK SMD ZERO ZERO DELAY DELAY BUFFER BUFFER 33.3 33.
GR-UT699 Development Board User Manual 2.9 Power Supply and Voltage Regulation The board operates from a single +5V DC power supply input. On board regulators generate the following voltages: +3.3V for the UT699 I/O voltage, memory chip and other peripherals • +2.5V for UT699 Vcore voltage REGULATOR JP14 Vcore (+2.5V for UT699RH core) REGULATOR JP13 1 JP15 +3V3asic (+3.3V for UT699RH) 2 JP12 +3.3V 3 CPCI CONNECTOR • +5V PCI 1 +3.3V PCI 2 3 n.c.
4 ETH_RXD[3..0] 4 ETH_TXD[3..0] GR-UT699 Development Board User Manual ETH_RXERR ETH_RXDV ETH_TXER RJ45 ETH_TXEN ETH_CRS ETH_COL UT699RH ETHERNET PHY ETH_MDIO ETH_MDC ETH_MDINT ETH_CLK ETH_RXCLK 25MHz ETH_TXCLK Figure 2-11: Block diagram of Ethernet Interface 2.11 PCI Interface The UT699RH ASIC incorporates a 33MHz/32 bit interface with 8 channel PCI Arbiter and is capable of being configured to be installed in either the SYSTEM slot (HOST) or in PERIPHERAL slots (GUEST).
GR-UT699 Development Board User Manual 2.11.1 Host/System Slot Configuration When installed in the System slot, the board provides the PCI arbitration and distributes the required PCI clocks to the backplane, and to the PCI interface in the FPGA.
GR-UT699 Development Board User Manual necessary to ensure that this pin is driven by the host slot. This can be achieved by installing jumper JP18 on the board, so that the board system reset signal RESETN provides the drive for the PCIRSTN signal. If the jumper is not installed, a weak (22k) pull up will pull the PCIRSTN signal high. 2.11.
GR-UT699 Development Board User Manual 2.12 Other Interfaces and Circuits 2.12.1 GPIO The 16 general Purpose Input Output signals of the ASIC (3.3V LVTTL voltage levels) are connected to a set of 0.1” pitch pin header connector on the front panel thus allowing easy access to these signals. A series protection resistor of 470 Ohm is included on each signal at the front panel connector.
GR-UT699 Development Board User Manual generating a system reset in the event of a software malfunction or crash. On this development board the WDOGN signal is connected as shown in the Figure 2-15 to the Processor Supervisory circuit. FRONT PANEL LED RESETN UT699RH ASIC BOARD MOUNTED LED WDOGN RSTIN_N JUMPER JP1D 7-8 POWER-ON RESET CIRCUIT Figure 2-15: Watchdog configuration To utilise the Watchdog feature, it is necessary to appropriately set-up and enable the Watchdog timer.
GR-UT699 Development Board User Manual Figure 2-16: Mezzanine Connector Pin Number Ordering Please note that this pin ordering does not match exactly the pin ordering which you will find on the Tyco part datasheets for the Mezzanine board mating connectors. The reason for this is explained in more detail in the Technical Note, RD-4. Therefore please take care when designing your own mezzanine boards to take account of this pin ordering.
3 GR-UT699 Development Board User Manual SETTING UP AND USING THE BOARD The default status of the Jumpers on the boards is as shown in table Figure 3-1. In this configuration the board is set up as a PCI Host. For the meaning of the various jumpers, refer to Table 4-23 and RD 1.
GR-UT699 Development Board User Manual To perform software download and debugging on the processor, a link from the Host computer to the DSU interface of the board is necessary. A connection to the DSU of the board can be made using a USB cable (Type-A to Mini-AB connectors) from the Host PC to the USB-DSU connector on the front panel. Note, to use the USB-DSU interface you need to install the FTDI Virtual Com driver on the Host PC.
GR-UT699 Development Board User Manual Figure 3-1: GRMON Output Screenshot #1 © Aeroflex Gaisler AB March 2013, Rev. 0.
GR-UT699 Development Board User Manual Figure 3-2: GRMON Output Screenshot #2 © Aeroflex Gaisler AB March 2013, Rev. 0.
4 GR-UT699 Development Board User Manual INTERFACES AND CONFIGURATION 4.
GR-UT699 Development Board User Manual Figure 4-1: Front Panel View (pin 1 of connectors marked) © Aeroflex Gaisler AB March 2013, Rev. 0.
Pin Name GR-UT699 Development Board User Manual Comment 1 No connect 6 2 No connect TXD-1 Transmit pin 7 3 No connect RXD-1 Receive pin 8 No connect 4 No connect 9 5 No connect GND Ground Table 4-2: J1 UART-1 - Serial Interface (RS232) connections Pin Name Comment 1 TPFOP Output +ve 2 TPFON Output -ve 3 TPFIP Input +ve 4 TPFOC Output centre-tap 5 No connect 6 TPFIN Input -ve 7 TPFIC Input centre-tap 8 No connect Table 4-3: J2 RJ45-ETHERNET Connector Pin Name
Pin Name 1 GR-UT699 Development Board User Manual Comment No connect 6 2 7 3 GND Ground CAN1_L CAN Dominant Low CAN1_H CAN Dominant High GND Ground 8 No connect 4 No connect 9 5 No connect CANSHD1 Shield Table 4-5: J4A (upper connector) CANBUS-1 interface connections Pin Name 1 Comment No connect 6 2 7 3 DGND Ground CAN0_L CAN Dominant Low CAN0_H CAN Dominant High DGND Ground 8 No connect 4 No connect 9 5 No connect CANSHD0 Shield Table 4-6: J4B (lower connector)
Pin Name Comment 1 DIN1+ Data In +ve DIN1- Data In -ve SIN1+ Strobe In +ve SIN1- Strobe In -ve SHIELD Inner Shield SOUT1+ Strobe Out +ve SOUT1- Strobe Out -ve DOUT1+ Data Out +ve DOUT1- Data Out -ve 6 2 7 3 8 4 9 5 GR-UT699 Development Board User Manual Table 4-8: J6 SPW-1 interface connections Pin Name Comment 1 DIN2+ Data In +ve DIN2- Data In -ve SIN2+ Strobe In +ve SIN2- Strobe In -ve SHIELD Inner Shield SOUT2+ Strobe Out +ve SOUT2- Strobe Out -ve DOUT2+ Dat
FUNCTION ASIC pin GR-UT699 Development Board User Manual CONNECTOR PIN ASIC pin FUNCTION DGND DGND 1 120 +5V 2 119 +5V DGND 3 118 DGND -12V 4 117 -12V DGND 5 116 DGND +12V 6 115 +12V DGND 7 114 DGND D15 64 8 113 86 D7 52 9 112 74 10 111 +3.3V DGND D31 D23 +3.
FUNCTION ASIC pin GPIO0 191 1 GPIO1 192 3 GPIO2 193 5 GPIO3 194 7 GPIO4 196 9 GPIO5 197 11 GPIO6 198 13 GPIO7 199 15 GPIO8 254 17 GPIO9 255 19 GPIO10 256 21 GPIO11 257 23 GPIO12 259 25 GPIO13 260 27 GPIO14 261 29 GPIO15 262 31 +3.
Pin Name Comment 1 VDD +5V Power 2 DM Data Negative 3 DP Data Positive 4 ID Identifier 5 GND Ground GR-UT699 Development Board User Manual Table 4-14: J12 DSU-Serial over USB MiniAB Pin Name Comment +VE +5V Inner Pin, 5V, typically TBD A -VE GND Outer Pin Return Table 4-15: J13 POWER – External Power Connector Pin Name Comment 1 +5V +5V, typically TBD A 2 GND Ground 3 +12V +12V Not used 4 GND Ground Table 4-16: J14 POWER – External Power Connector © Aeroflex Gai
FUNCTION DGND D31 D30 D29 D28 +3.3V D27 D26 D25 D24 DGND SDDQM3 SDDQM2 +3.3V A2 A3 A4 DGND D23 D22 D21 D20 +3.3V D19 D18 D17 D16 DGND nc nc SDCLK0 +3.3V SDRASN SDWEN SDCSN0 SDCSN1 nc DGND nc nc +3.3V D15 D14 D13 D12 DGND D11 D10 D9 D8 +3.3V A8 A10 DGND A11 A12 +3.3V SDDQM1 SDDQM0 DGND D7 D6 D5 D4 +3.3V D3 D2 D1 D0 DGND SDSDA / pulled high +3.
GR-UT699 Development Board User Manual 4.2 List of Oscillators, Switches and LED's Name Function Description X1 OSC_MAIN Main oscillator for ASIC DIL8 socket, 3.3V (75MHz as standard) X2 OSC_ETH Oscillator for Ethernet PHY transceiver, SMD type, 3.3V, 25.000MHz X3 OSC_SPW DIL8 socket for user installed SPW Clock Oscillator, 3.3V Table 4-18: List and definition of Oscillators Name Function Description D1 POWER (3.
GR-UT699 Development Board User Manual FUNCTION ASIC pin OPEN SWITCH CLOSED PIO8 254 '1' 1 '0' PIO9 255 '1' 2 '0' PIO10 256 '1' 3 '0' PIO11 257 '1' 4 '0' PIO12 259 '1' 5 '0' PIO13 260 '1' 6 '0' PIO14 261 '1' 7 '0' PIO15 262 '1' 8 '0' Table 4-22: DIP Switch S4 'PIO[15..8]' definition 4.3 List of Jumpers Name Function Type Description JP1 CONFIG 4x2 pin 0.1” Header Header for DSU, PROM and WDOG enable JP2 ETH_INTR 2 pin 0.
GR-UT699 Development Board User Manual Figure 4-2: PCB Top View © Aeroflex Gaisler AB March 2013, Rev. 0.
GR-UT699 Development Board User Manual Figure 4-3: GR-UT699 Assembly Photo © Aeroflex Gaisler AB March 2013, Rev. 0.
