User manual

26 GR-LEON4-ITX Development Board
User Manual
the Processor Supervisory circuit.
To utilise the Watchdog feature, it is necessary to appropriately set-up and enable the
Watchdog timer. Please consult the LEON4 ASIC data sheet (RD-4) for the correct register
locations and details.
Also, to allow the WDOGN signal to generate a system reset it is necessary to install the
Jumper JP2 (see Figure 2-20).
For software development it is often convenient or necessary to disable the Watchdog
triggering in order to be able to easily debug without interference from the Watchdog
operation. In this case, the Jumper JP2 should be removed. When the watchdog triggers, a
system reset will not occur.
JTAG interface
Two connectors on the back edge of the PCB provide the possibility to connect to the JTAG
signals and JTAG chain of the LEON4 ASIC.
This interface allows DSU Debug over the JTAG interface to be performed.
Two connectors are provided, J20, a 14 pin 2mm Molex connector for connection with ribbon
cable to a JTAG cable such as the Xilinx Parallel IV or Platform USB cable, and J19, which
is a 6 pin 0.1” header which can be used to connect to Parallel III style cables.
eASIC SPI Configuration Interface
In order to store configuration bit information for the EASIC structured ASIC a dedicated SPI
PROM (U2) is provided on the board with its own 6 pin header for programming (J24).
This configuration information is automatically read out of the PROM by the ASIC when the
board is powered up in order to bring the ASIC into full operation.
When programming the SPI Configuration Prom, the jumpers JP11 must be removed in
order to 'disconnect' the prom form the ASIC. In normal use the jumpers JP11 should be
installed 1-2, 3-4, 5-6, 7-8 so that the correct communication can occur between the ASIC
and PROM.
The configuration prom will normally be pre-programmed during manufacture/test of the
board, and since these parameters are not user accessible, the functioning and
programming of this prom are not further described in this document.
© Aeroflex Gaisler AB August 2010, Rev. 0.3
Figure 2-20: Watchdog configuration
JUMPER
JP2
JUMPER
JP2
LEON4
ASIC
LEON4
ASIC
POWER-ON
RESET
CIRCUIT
POWER-ON
RESET
CIRCUIT
RESETN WDOGN RSTIN_N