User manual

23 GR-LEON4-ITX Development Board
User Manual
© Aeroflex Gaisler AB August 2010, Rev. 0.3
Figure 2-17: Board level Clock Distribution Scheme
ZERO
DELAY
BUFFER
ZERO
DELAY
BUFFER
19.2 MHz
19.2 MHz
CLK_MAIN
SMD
LEON4
ASIC
PCI_CLK
50 MHz
50 MHz
SMD
TBD MHz
TBD MHz
DIL8 SOCKET
DDR2CLK
CLK_50MHz
33.3 MHz
33.3 MHz
SDRAM
MODULE
SDRAM
MODULE
SMD
DDR2 RAM
ZERO
DELAY
BUFFER
ZERO
DELAY
BUFFER
USB-PHY
USB-PHY
USB-PHY
USB-PHY
USB-PHY
USB-PHY
USB-PHY
USB-PHY
USB-PHY
USB-PHY
PCI-SLOT
PCI-SLOT
PCI-SLOT
PCI-SLOT
USB-PHY
USB-PHY
ETH-PHY
ETH-PHY
ETH-PHY
ETH-PHY
USBHC0_CLK
USBHC1_CLK
USBDC_CLK
USBDCL_CLK