GR-LEON4-ITX Development Board User Manual AEROFLEX GAISLER AB Rev. 0.
GR-LEON4-ITX Development Board User Manual Information furnished by Aeroflex Gaisler AB is believed to be accurate and reliable. However, no responsibility is assumed by Aeroflex Gaisler AB for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Aeroflex Gaisler AB.
GR-LEON4-ITX Development Board User Manual TABLE OF CONTENTS 1 INTRODUCTION...........................................................................................................7 1.1 1.2 1.3 1.4 2 Overview...................................................................................................................... 7 References...................................................................................................................9 Handling.......................................
GR-LEON4-ITX Development Board User Manual LIST OF TABLES Table 3-1: Default Status of Jumpers/Switches..............................................................................26 Table 4-1: List of Connectors......................................................................................................... 27 Table 4-2: PCI-J1 PCI Connector Slot 0.........................................................................................30 Table 4-3: PCI-J2 PCI Connector Slot 1..................
GR-LEON4-ITX Development Board User Manual Figure 2-13: SPI Interface Configuration........................................................................................19 Figure 2-14: PIO interface configuration........................................................................................19 Figure 2-15: Debug Support Unit connections................................................................................20 Figure 2-16: Board level Clock Distribution Scheme...........................
GR-LEON4-ITX Development Board User Manual Intentionally Blank © Aeroflex Gaisler AB August 2010, Rev. 0.
1 GR-LEON4-ITX Development Board User Manual INTRODUCTION 1.1 Overview This document describes the GR-LEON4-ITX Development Board. The purpose of this equipment is to provide developers with a convenient hardware platform for the evaluation and development of software for the Aeroflex Gaisler LEON4 Processor. The LEON4 processor is a synthesizable VHDL model of a 32-bit processor compliant to the SPARC V8 architecture.
GR-LEON4-ITX Development Board User Manual The PCB contains the following main items as detailed in section 2 of this document: • LEON4 ASIC with Dual Core Leon4 architecture • Memory • DDR2-400 RAM 256 MByte • SPI program FLASH 64Mbit (2x 1Gbit HYB18T1G160BF-5) (1x M25P64 SPI prom) • Power, Reset, Clock and Auxiliary circuits • Interface circuits required for the features listed below The interface connectors on the Front edge of the board provide: • Dual PCI (32 bit) mother-board slots • D
GR-LEON4-ITX Development Board User Manual Debug interface support is demonstrated on the board with support for debugging via the following interfaces: • • • • JTAG ETH (EDCL) USB (USB-DCL) SERIAL (LVTTL i/f) 1.2 References RD-1 GR-LEON4-ITX_schematic.pdf, Schematic RD-2 GR-LEON4-ITX_assy_drawing.pdf, Assembly Drawing RD-3 GR-LEON4-ITX_bom.pdf, Bill of Materials RD-4 LEON4-ASIC-DEMO Data Sheet and User's Manual RD-5 GRMON User Manual RD-6 GR-LEON4-ITX Quick Start Guide 1.
2 GR-LEON4-ITX Development Board User Manual ELECTRICAL DESIGN 2.1 LEON4 ASIC The Aeroflex Gaisler LEON4 processor core is a synthesizable VHDL model of a 32-bit processor compliant with the SPARC V8 architecture. The core is highly configurable and particularly suitable for high performance multi-core system-on-a-chip (SOC) designs. The core is interfaced using the AMBA 2.0 AHB bus and supports the IP core plug&play method provided in the Aeroflex Gaisler IP library (GRLIB).
GR-LEON4-ITX Development Board User Manual Figure 2-2: LEON4 SOC Block Diagram This LEON4 ASIC is packaged in a 672-pin, 1mm pitch Flip Chip Ball Grid Array package , and is soldered on to the PCB. Details of the interfaces, operation and programming of the LEON4 ASIC is given in the LEON4-ASIC-DEMO Data sheet and User's Manual, RD-4, and in RD-5. Figure 2-3: LEON4-ASIC-DEMO © Aeroflex Gaisler AB August 2010, Rev. 0.
GR-LEON4-ITX Development Board User Manual 2.2 Board Block Diagram The GR-LEON4-ITX Board provides the electrical functions and interfaces as represented in the block diagram, Figure 2-4. MOUSE/ KEYB I/F PS/2 I/F VIDEO I/F DVI TRANSCEIVER USB - DSU USB 2.0 DSU I/F USB-B DEVICE I/F USB 2.0 DEVICE I/F USB 2.
GR-LEON4-ITX Development Board User Manual 2.4 PCI Slots The LEON4 ASIC device incorporates a GRPCI Fast 32-bit PCI bridge core which functions as the PCI Host Controller on the LEON4-ITX Board. To allow this board to function as a PCI motherboard, this board includes two 32 bits, 33MHz PCI motherboard slot connectors, PCI-J1 and PCI-J2. Note that the PCI slots are intended for cards which are compatible with 3.3V PCI signalling voltage levels. 2.
GR-LEON4-ITX Development Board User Manual The host interfaces include a MIC2025USB power switch component, controlled to provide 5V power output to the Dual USB-A style connector on the board. Please refer to the device data sheet of the ISP1504A device for further information. NEXT DP STP DM DIR ASIC ASIC DATA[7..0] USB INTERFACE USB USBAA ISP1504A ISP1504A USB USBPHY PHY RESETN_N ENABLE POWER POWER SWITCH SWITCH CLK (60MHz) XTAL XTAL 19.2MHz 19.
GR-LEON4-ITX Development Board User Manual DVI_CLK_P & N TFT_LCD_CLK_P DVI_D1_P & N TFT_LCD_DATA[11..0] DIGITAL VGA DVI_D0_P & N TFT_LCD_CLK_N DVI_D2_P & N ASIC ASIC TFT_LCD_VSYNC VIDEO INTERFACE CH7301C CH7301C DVI DVICONTROLLER CONTROLLER RED GREEN TFT_LCD_DE BLUE HSYNC TFT_LCD_RESET ANALOG VGA TFT_LCD_HSYNC VSYNC DVI-I FEMALE Figure 2-7: DVI Video Interface 2.
GR-LEON4-ITX Development Board User Manual SUB-D 9 pin Female TXD RS232 DRIVER/ RECEIVERS ASIC RS232 INTERFACE RXD Figure 2-9: Serial interface The included ribbon cables providing a DE-9 connector should be connected as shown in figure 2-10 (the red stripe should be toward the label UART-1/UART-2). Figure 2-10: Serial interface 2.12 Serial Debug Support Interface (LVTTL) A 10 pin 0.
CAN CAN TRANSCEIVER TRANSCEIVER TXD RXD CAN_L CAN_H CAN CAN TRANSCEIVER TRANSCEIVER CAN_L CAN interface 1 CONTROLLER LOGIC IN ASIC RXD CAN_H CAN interface 0 TXD GR-LEON4-ITX Development Board User Manual Figure 2-11: Block Diagram of the CAN interface Configuration of Bus Termination The CAN interfaces on the board can be configured for either end node or stub-node operation by means of the jumpers JP8 and JP7 for interface 0 and 1 respectively, as shown in Figure 2-12.
GR-LEON4-ITX Development Board User Manual Figure 2-12: Transceiver and Termination Configuration (one of 2 interfaces shown) Configuration of Slew Rate The SN65HVD230 transceiver device used on the board has the facility to set the device into STANDBY mode, by connecting an active high external signal to pin 8 of the device. On this board, this pin is connected to the CAN_ENable contorl pin of the ASIC.
GR-LEON4-ITX Development Board User Manual C75 DGND +3V3 +3V3 I2 C I2 C M 0 SCL SDA I2 C M 0 _ S C L I2 C M 0 _ S D A U15 VCC R ST SCL SDA X1 X2 VB GND Y1 3 2 .7 6 8 k 1 2 3 4 2 +3V3 TP6 8 7 6 5 1 R23 10k R24 10k 3 4 100n + DGND DS 1672 I2 C R e a l T im e C lo c k c h ip w ith p o w e r b a c ku p C76 0 .
GR-LEON4-ITX Development Board User Manual +3V3 M e m o ry SPI S P IM _ C L K S P IM _ M O S I S P IM _ M IS O S P IM _ S E L SPI S P IC _ C S [1 ..0 ] S P IC _ M IS O S P IC _ M O S I S P IC _ S C K S P IC _ S E L S S S S P P P P IM _ C L K IM _ M O S I IM _ M IS O IM _ S E L S S S S S P P P P P IC IC IC IC IC R 43 10k _ C S [1 ..
GR-LEON4-ITX Development Board User Manual 2.17 Debug Support Unit Interfaces Program download and debugging to the processor is performed using the GRMON Debug Monitor tool from Aeroflex Gaisler (RD-5). The LEON4 ASIC provides a interface for Debug and control of the processor by means of a host terminal via its DSU interface, as represented in Figure 2-16.
GR-LEON4-ITX Development Board User Manual 2.18 Other Auxiliary Interfaces and Circuits Oscillators and Clock Inputs The oscillator and clock scheme for the GR-LEON4-ITX Board is shown in Figure 2-17. The main oscillator for the GR-LEON4-ITX ASIC is a 50 MHz Crystal oscillator. This oscillator is an SMD oscillator soldered on to the board and a zero-delay buffer circuit (CY2305) is used to distribute this 50MHz clock signal. Addtionally, oscillators are provided as follows: • 33.
ETH-PHY ETH-PHY GR-LEON4-ITX Development Board User Manual LEON4 ASIC ETH-PHY ETH-PHY 50 50MHz MHz ZERO ZERO DELAY DELAY BUFFER BUFFER CLK_50MHz SMD DDR2CLK DDR2 SDRAM RAM SDRAM MODULE MODULE CLK_MAIN TBD TBDMHz MHz DIL8 SOCKET 19.2 19.2MHz MHz ZERO ZERO DELAY DELAY BUFFER BUFFER SMD USB-PHY USB-PHY USBHC0_CLK USB-PHY USB-PHY USBHC1_CLK USB-PHY USB-PHY USBDC_CLK USB-PHY USB-PHY USBDCL_CLK PCI_CLK 33.3 33.
GR-LEON4-ITX Development Board User Manual Figure 2-18: Clock and PLL organisation inside LEON4 ASIC © Aeroflex Gaisler AB August 2010, Rev. 0.
GR-LEON4-ITX Development Board User Manual Power Supply and Voltage Regulation The board operates from a single +5V DC power supply input. On board regulators generate the following voltages: • +3.3V for the GR-LEON4-ITX I/O voltage, interfaces and other peripherals • +2.5V for LEON4 configuration voltage • +1.8V for DDR2 supply voltage • +1.2V for LEON4 Vcore voltage REGULATOR +3V3 REGULATOR +1.2V (Vcore) +1.8V (Vddr2) +2.
GR-LEON4-ITX Development Board User Manual the Processor Supervisory circuit. RESETN LEON4 LEON4 ASIC ASIC WDOGN RSTIN_N JUMPER JUMPER JP2 JP2 POWER-ON POWER-ON RESET RESET CIRCUIT CIRCUIT Figure 2-20: Watchdog configuration To utilise the Watchdog feature, it is necessary to appropriately set-up and enable the Watchdog timer. Please consult the LEON4 ASIC data sheet (RD-4) for the correct register locations and details.
3 GR-LEON4-ITX Development Board User Manual SETTING UP AND USING THE BOARD The default status of the Jumpers on the boards is as shown in Table 3-1. For the meaning of the various jumpers, refer to Table 4-3 and RD 1. Jumper JP1 Jumper Setting Installed 1-2 J10 Installed 17-18 JP11 Installed 1-2, 3-4, 5-6, 7-8 Comment Connects 50MHz Main Oscillator for main CLK This inserts a pull-up on GPIO43 to enable USB-DCL on power up.
4 GR-LEON4-ITX Development Board User Manual INTERFACES AND CONFIGURATION 4.
GR-LEON4-ITX Development Board User Manual Figure 4-1: Front Panel View (pin 1 of connectors marked) © Aeroflex Gaisler AB August 2010, Rev. 0.
GR-LEON4-ITX Development Board User Manual Figure 4-2: Board Connector View © Aeroflex Gaisler AB August 2010, Rev. 0.
GR-LEON4-ITX Development Board User Manual P C I-J 1 P C I_ T C K -1 2 V DGND P C I_ IN T B P C I_ IN T D P C I_ C L K A P C I_ A R B _ R E Q 0 +5V +5V DGND DGND P C I_ A D 3 1 P C I_ A D 2 9 P C I_ A D 2 7 P C I_ A D 2 5 P C I_ C B E 3 P C I_ A D 2 3 P C I_ A D 2 1 P C I_ A D 1 9 P C I_ A D 1 7 P C I_ C B E 2 P C I_ IR D Y P C I_ D E V S E L P C I_ L O C K P C I_ P E R R P C I_ S E R R P C I_ C B E 1 P C I_ A D 1 4 P C I_ A D 1 2 P C I_ A D 1 0 DGND +3V3PC I DGND +3V3PC I DGND +3V3PC I DGND +3V
GR-LEON4-ITX Development Board User Manual P C I-J 2 P C I_ T C K -1 2 V DGND P C I_ IN T C P C I_ IN T A P C I_ C L K B P C I_ A R B _ R E Q 1 P C I_ A D 3 1 P C I_ A D 2 9 P C I_ A D 2 7 P C I_ A D 2 5 P C I_ C B E 3 P C I_ A D 2 3 P C I_ A D 2 1 P C I_ A D 1 9 P C I_ A D 1 7 P C I_ C B E 2 P C I_ IR D Y P C I_ D E V S E L P C I_ L O C K P C I_ P E R R P C I_ S E R R P C I_ C B E 1 P C I_ A D 1 4 P C I_ A D 1 2 P C I_ A D 1 0 +5V +5V DGND DGND +3V3PC I DGND +3V3PC I DGND +3V3PC I DGND +3V3PC I D
Pin Name Comment 1 TPFOP Output +ve 2 TPFON Output -ve 3 TPFIP Input +ve 4 TPFOC Output centre-tap 5 GR-LEON4-ITX Development Board User Manual No connect 6 TPFIN Input -ve 7 TPFIC Input centre-tap 8 No connect Table 4-4: J3A (Top) RJ45 10/100Mbit/s Ethernet Connector 1 Pin Name Comment 1 TPFOP Output +ve 2 TPFON Output -ve 3 TPFIP Input +ve 4 TPFOC Output centre-tap 5 No connect 6 TPFIN Input -ve 7 TPFIC Input centre-tap 8 No connect Table 4-5: J3B (Bo
Pin Name Comment 1 VBUS +5V (from external host) 2 DM Data Minus 3 DP Data Plus 4 DGND Ground GR-LEON4-ITX Development Board User Manual Table 4-9: J6 USB type B connector – USB Debug Communication Link Pin Name Comment 1 Data 2- Digital red - (Link 1) 2 Data 2+ Digital red + (Link 1) 3 Data 2/4 shield 4 Data 4- Digital green - (Link 2) - not connected on this board 5 Data 4+ Digital green + (Link 2) - not connected on this board 6 DDC clock 7 DDC data 8 Analog vert
Pin Name ASIC Comment Pin 1 MOUSE_DATA E19 2 nc No connect 3 DGND Ground 4 V+ +5V 5 MOUSE_CLK 6 nc D19 GR-LEON4-ITX Development Board User Manual Data in Clock out No connect Table 4-11: J8A (Top) PS2 Connector - Mouse Pin Name ASIC Comment Pin 1 KEYB_DATA B19 2 nc No connect 3 DGND Ground 4 V+ +5V 5 KEYB_CLK 6 nc A19 Data in Clock out No connect Table 4-12: J8B (Bottom) PS2 Connector – Keyboard FUNCTION ASIC pin CONNECTOR PIN GPIO0 A13 1 GPIO2 C13 3
FUNCTION ASIC pin GR-LEON4-ITX Development Board User Manual CONNECTOR PIN SPIC_CS0 A24 1 SPIC_MOSI B23 2 SPIC_SCK A22 3 DGND 4 +3V3 5 ■ □ □ □ □ □ □ □ □ □ ASIC pin FUNCTION 6 B24 SPIC_CS0 7 A23 SPIC_MISO 8 C22 SPIC_SEL 9 DGND 10 +3V3 Table 4-15: J11- SPI Header for User SPI interface FUNCTION ASIC pin nc CONNECTOR PIN 1 DSUTX A20 2 DSURX G21 3 nc 4 DGND 5 ■ □ □ □ □ □ □ □ □ □ FUNCTION 6 nc 7 nc 8 nc 9 nc 10 CHASSIS Table 4-16: J12 - UART-DSU H
FUNCTION GR-LEON4-ITX Development Board User Manual CONNECTOR PIN nc 1 CAN0_L 2 DGND 3 nc 4 CANSHD 5 ■ □ □ □ □ □ □ □ □ □ FUNCTION 6 DGND 7 CAN0_H 8 nc 9 nc 10 CHASSIS Table 4-20: J16 -CAN-0 Header for CANBUS-0 signals FUNCTION ASIC pin CONNECTOR PIN FUNCTION I2CS_SCL F26 1 I2CS_SDA F24 3 ■ □ □ □ 2 +3V3 4 DGND Table 4-21: J17 -I2C Slave Pin connections for User I2C interface FUNCTION ASIC pin CONNECTOR PIN FUNCTION I2CM1_SCL E24 1 I2CM1_SDA E23 3 ■ □ □
Pin Name Comment 1 DGND Ground VREF 3.3V DGND Ground TMS JTAG: TMS DGND Ground TCK JTAG: TCK DGND Ground TDO JTAG: TDO DGND Ground TDI JTAG: TDI DGND Ground NC No connect DGND Ground NC No connect 2 3 4 5 6 7 8 9 10 11 12 13 14 GR-LEON4-ITX Development Board User Manual Table 4-24: J20 -JTAG signal interface Pin Name Comment 1 +3V3 Provides 3.3V to PCI slots 2 +3V3 Provides 3.
Pin Name Comment +VE +5V Inner Pin, 5V, typically TBD A -VE GND Outer Pin Return GR-LEON4-ITX Development Board User Manual Table 4-26: J22 -POWER +5V DC power input connector Pin Name Comment 1 V+ 3.3V 2 DGND Ground 3 TCK JTAG: TCK 4 TDO JTAG: TDO 5 TDI JTAG TDI 6 TMS JTAG: TMS Table 4-27: J23 -ASIC-JTAG JTAG interface Pin Name Comment 1 V+ 3.
GR-LEON4-ITX Development Board User Manual Name Function Description D1 POWER (3.3V) Power indicator D2 ERRORN Leon processor in 'ERROR' mode D3-D10 GPIO[27..34] LED indicators for GPIO[27..
GR-LEON4-ITX Development Board User Manual Figure 4-3: PCB Top View © Aeroflex Gaisler AB August 2010, Rev. 0.
GR-LEON4-ITX Development Board User Manual Figure 4-4: GR-LEON4-ITX Assembly Photo (Top View) © Aeroflex Gaisler AB August 2010, Rev. 0.
