User manual

61 TPC-1071H/1271H/1571H/1771H User Manu-
Appendix B Built-in DIO Module Setting
B.4.5 DIO register format of FPGA code
Embedded Platform PCI Digital I/O
Base Address 0 R/W BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0
Base Address 0 +
00H ~ 1EH
Reserved
Base Address 0 +
1FH
R
FPGA Code Revision
D7 D6 D5 D4 D3 D2 D1 D0
Embedded Platform PCI Digital I/O
Base Address 1 R/W BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0
Base Address 1 + 00H
R
DI
DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0
W
DI
Base Address 1 + 01H
R
DO
DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0
W
DO
DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0
Base Address 1 + 02H
R
Interrupt Enable Status
DI1EN DI0EN
W
Interrupt Enable Register
DI1EN DI0EN
Base Address 1 + 03H
R
Interrupt Triggering Status
DI1RF DI0RF
W
Interrupt Triggering Register
DI1RF DI0RF
Base Address 1 +
04H~06H
Reserved
Base Address 1 + 07H
R
Interrupt Flag Status
DI1IF DI0IF
W
Interrupt Flag Clear Register
DI1IFCL DI0IFCL
Base Address 1 +
08H~10H
Reserved
Base Address 1 + 11H
R
Buzzer Status
SPKS1 SPKSP0 SPKEN
W
Buzzer Register
SPKSPSSPKSPS0 SPKEN