User manual

PCL-818 Series User Manual 42
Appendix B Block Diagram
B.1 PCL-818HD/HG
B.2 PCL-818L
8254
Counter # 0
Counter # 1
Counter # 2
CLK 1
CLK 2
Out 1
Out 2
Address Bus
PC BUS
DMA Signals
IRQ Signals
EOC
Ext Trig
Analog
Input
12-bit A/D
Converter
Sample
& Hold
Prog. Gain
Amplifer
1 K Word
FIFO
Control/Status
Logic
Counter 0 CLK
Counter Gate
10MHz
OSC
Divider
100KHz
1MHz
10MHz
:
Register
Select
Status
Address
Decoder
Data
Buffer
CPLD
Intermal Data Bus
D/A Output
Digital
Input
Digital
Output
16-bit
Digital Out
:
16-bit
Digital In
12-bit D/A
Converter
:
MUX
16 S/E
or
8 Diff
:
.
Channel
Scan Logic
Trigger
Logic
Data
MUX
RAM
DMA
Logic
IRQ
Logic
8254
Counter # 0
Counter # 1
Counter # 2
CLK 1
CLK 2
Out 1
Out 2
Address Bus
PC BUS
Ext Trig
Analog
Inp ut
Counter 0 CLK
Counter Gate
10MHz
OSC
Divider
100KHz
1MHz
10MHz
:
Register
Select
Status
Address
Decoder
CPLD
Interm al D a ta B us
D/A Output
Digital
Input
Digital
Output
:
:
:
.
Channel
Scan Logic
Trigger
Logic
Data
MUX
DMA
Logic
IRQ
Logic
EOC
12-bit A/D Converter
with
Sam ple a n d H o ld
Prog. Gain
Am plifer
RAM
MUX
16 S/E
or
8 Diff.
16-bit
Digital Out
16-bit
Digital In
12-bit D/A
Converter
Data
Buffer
DMA Signals
IRQ Signals