User manual

47 Appendix A
A.2 Analog Input
Channels 4 single-ended analog input channels
Resolution 12-bit FIFO Size 32k
Max. Sampling Rate
30 MHz
Input range and
Gain List
Gain 1 2 5 10
Range ±5V ±2.5V ±1V ±0.5V
Drift Gain 1 2 5 10
Zero
(µV / °C)
±200 ±100 ±40 ±20
Gain
(ppm / °C)
±30 ±30 ±30 ±30
Small Signal Band-
width for PGA
Gain 1 2 5 10
Bandwidth
(-3dB)
7MHz 7MHz 7MHz 7MHz
Max. Input voltage ±15 V Input Surge Protection 30 Vp-p
Input Impedance 50/1M/Hi Z jumper selectable /100pF
Trigger Mode Software, pacer, post-trigger, pre-trigger, delay-trigger, about-trigger
Accuracy DC DNLE ±1LSB (No Missing Codes:12 Bits Guaranteed)
INLE ±2LSB
Offset error Adjustable to ±1LSB
Gain error Adjustable to ±1LSB
AC SINAD S/
(N+D)
66 dB (Hi Z)
ENOB 10.67 bits (Hi Z)
THD -73 dB (Hi Z)
External Clock 1 Logic level TTL (Low: 0.8 V max. High: 2.0V min.)
Input
Impedance
Hi Z
Input coupled DC
Frequency Up to 10MHz
External Clock 0 Logic level 5.0V peak to peak sin wave
Input
Impedance
Hi Z
Input coupled AC
Frequency Up to 10MHz
External Trigger 0 Logic level TTL (Low: 0.8 V max. High: 2.0V min.)
Input
Impedance
Hi Z
Input coupled DC
External Analog
Trigger Input
Range By analog input range
Resolution 8-bit
Frequency Up to 1MHz