User manual

33 Chapter 4
4.3.1 Internal A/D Sample Clock
The internal A/D sample clock uses a 60 MHz time base. Conversions
start on the rising edge of the counter output. You can use software to
specify the clock source as internal and the sampling frequency to pace
the operation. The minimum frequency is 234375 S/s, the maximum fre-
quency is 30 MS/s. According to the sampling theory (Nyquist Theorem),
you must specify a frequency that is at least twice as high as the input’s
highest frequency component to achieve valid sampling. For example, to
accurately sample a 300 kHz signal, you have to specify sampling fre-
quency of at least 600 kHz. This consideration can avoid an error condi-
tion often know as aliasing, in which high frequency input components
appear erroneously as lower frequencies when sampling.
4.3.2 External A/D Sample Clock 0
The external sample clock 0 is a sine wave signal source which is con-
verted to a TTL signal inside the PCIE-1744. This signal is AC coupled.
The input impedance of the external clock 0 is 50 ohms and the input
level is 5 volts peak-to-peak.
Please note that the frequency of the external clock is the system clock.
The maximum A/D clock frequency is half of the system clock.
4.3.3 External A/D Sample Clock 1
The external sample clock 1 is a digital clock. The input impedance is 50
ohms and the input level should be 2V~5V into the 50-ohm load. This
signal is DC coupled.
Figure 4.5: PCIE-1744 Sample Clock Sources