User manual

29 PCI-1762 User Manual
Appendix C Register Structure and Format
C.7 Interrupt Control Register - BASE+6H and
BASE+7H
The Interrupt Control Register control the status of two interrupt signal sources (IDI0
and IDI8). The user can clear the interrupt by writing its corresponding value to the
Interrupt Control Register, as shown in below table.
IDnCLR Interrupt clear control bits (n = 0 or 8)
This bit must first be cleared to service the next inter
rupt.
0 Don't care
1 Clear the interrupt
IDnEN Interrupt enable control bits (n = 0 or 8)
Set this bit to Enable/Disable the interrupt.
0 Disable
1 Enable
IDnRF Interrupt triggering control bits (n = 0 or 8)
The interrupt can be triggered by a rising edge or falling
edge of the interrupt signal, as determined by the value in
this bit.
0 Rising edge trigger
1 Falling edge trigger
Appendix A
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Table C.6: Register for Interrupt Control
Write Interrupt Control Register
Bit # 76543210
BASE +7 ID8RF ID8EN ID8CLR
BASE +6 ID0RF ID0EN ID0CLR