Specifications

Appendix C
– 32 –PCI-1762 User’s Manual
Advantech Co., Ltd.
www.advantech.com
C.7 Interrupt Control Register - BASE+6 and BASE+7
The Interrupt Control Register control the status of two interrupt
signal sources (IDI0 and IDI8). The user can clear the interrupt by
writing its corresponding value to the Interrupt Control Register, as
shown in below table.
Table C-7: Register for interrupt control
IDnCLR Interrupt clear control bits (n = 0 or 8).
This bit must first be cleared to service the next
interrupt.
0 Don’t care
1 Clear the interrupt
IDnEN Interrupt enable control bits (n = 0 or 8)
Set this bit to Enable/Disable the interrupt.
0 Disable
1 Enable
IDnRF Interrupt triggering control bits (n = 0 or 8)
The interrupt can be triggered by a rising edge or
falling edge of the interrupt signal, as determined by
the value in this bit.
0 Rising edge trigger
1 Falling edge trigger
Write
Interrupt Control Register
Bit # 7 6 5 4 3 2 1 0
BASE + 7 ID8RF ID8EN ID8CLR
BASE + 6 IDORF IDOEN ID0CLR