Specifications

Appendix C
– 31 – PCI-1762 User’s Manual
Advantech Co., Ltd.
www.advantech.com
C.6 Interrupt Status Register - BASE+6 and BASE+7
The Interrupt Status Register control the status of two interrupt signal
sources (IDI0 and IDI8).
Table C-6: Register for interrupt status
IDnF Interrupt flag bits (n = 0 or 8)
This bit is a flag indicating the status of an interrupt.
User can read this bit to get the status of the
interrupt
0 No interrupt
1 Interrupt occurred
IDnEN Interrupt enable control bits (n = 0 or 8)
Read this bit to Enable/Disable the interrupt.
0 Disable
1 Enable
IDnRF Interrupt triggering control bits (n = 0 or 8)
The interrupt can be triggered by a rising edge or
falling edge of the interrupt signal, as determined by
the value in this bit.
0 Rising edge trigger
1 Falling edge trigger
Read Interrupt Status Register
Bit # 7 6 5 4 3 2 1 0
BASE + 7 ID8RF ID8EN ID8F
BASE + 6 IDORF IDOEN ID0F