User`s manual

22 PCI-1753 User's Manual
Table 3-2: Interrupt control register bit map
Mn0 and Mn1: “mode bits” of port Cn (n = 0 ~ 3)
M1: pattern match port enable control bit of port A0
M2: change of state port enable control bit of port B0
En: triggering edge control bit (n = 0 ~ 3)
Fn: interrupt flag bit of port Cn (n = 0 ~ 3)
F01: pattern patch interrupt flag bit of port A0
F02: change of state interrupt flag bit of port B0
Base+16/48 Port 0
Bit # D7 D6 D5 D4 D3 D2 D1 D0
Abbreviation F0 E0 M01 M00 F02 M2 F01 M1
Base+17/49 Port 1
Bit # D7 D6 D5 D4 D3 D2 D1 D0
Abbreviation F1E1M11M10----
Base+18/50 Port 2
Bit # D7 D6 D5 D4 D3 D2 D1 D0
Abbreviation F2E2M21M20----
Base+19/51 Port 3
Bit # D7 D6 D5 D4 D3 D2 D1 D0
Abbreviation F3E3M31M30----