PCI-1753/1753E 96/192-bit Digital I/O Card User's manual
Copyright This documentation and the software included with this product are copyrighted 1999 by Advantech Co., Ltd. All rights are reserved. Advantech Co., Ltd. reserves the right to make improvements in the products described in this manual at any time without notice. No part of this manual may be reproduced, copied, translated or transmitted in any form or by any means without the prior written permission of Advantech Co., Ltd. Information provided in this manual is intended to be accurate and reliable.
Contents CHAPTER 1 General Information ......................... 1 1.1 Introduction ........................................................... 2 1.2 Features .................................................................. 4 1.3 Applications ........................................................... 4 1.4 Specifications ....................................................... 5 1.5 Pin Assignments ..................................................... 6 1.6 Block Diagram ..................................
3.3.3 Interrupt Control Registers .................................................................... 21 3.3.4 Interrupt Source Control ........................................................................ 24 3.3.5 Interrupt Triggering Edge Control .......................................................... 25 3.3.6 Interrupt Flag Bit ................................................................................... 25 3.3.7 Pattern Match Interrupt Function ..............................................
CHAPTER 1 General Information
1.1 Introduction The PCI-1753 is a 96-bit digital I/O card for the PCI bus, which can be extended to 192 digital I/O channels by connecting with its extension board, PCI-1753E. The card emulates mode 0 of the 8255 PPI chip, but the buffered circuits offer a higher driving capability than the 8255. The 96 I/O lines are divided into twelve 8-bit I/O ports: A0, B0, C0, A1, B1, C1, A2, B2, C2, A3, B3 and C3. Users can configure each port as input or output via software.
1753/PCI-1753E controls how these signals generate an interrupt. More than one interrupt request signals can be generated at the same time, and then the software can process these request signals by ISR. The multiple interrupt sources provide the card with more capability and flexibility. The PCI-1753/1753E also provides “Pattern Match” interrupt function for port A0. The card monitors the states of port A0 and compares them with a pre-set pattern.
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1.4 Specifications I/O Channels 96 digital I/O lines (PCI-1753 only) 192 digital I/O lines (using PCI-1753E extension) Programming Mode 8255 PPI mode 0 Input Signal Logic level 0: 0.8 V max. Logic level 1: 2.0 V min. Output Signal Logic level 0: 0.44 V max. @ 24 mA (sink) Logic level 1: 3.76 V min. @ 24 mA (source) Transfer Rate 1.6 Mbytes/sec (tested under DOS, K6 300MHz CPU) Power Consumption +5 V @ 400 mA (typical) +5 V @ 2.7 A (max.
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CHAPTER Installation 2 Chapter 2 Installation 9
2.1 Initial Inspection Before starting to install the PCI-1753/1753E, make sure there is no visible damage on the card. We carefully inspected the card both mechanically and electrically before shipment. It should be free of marks and in perfect order on receipt. As you unpack the PCI-1753/1753E, check it for signs of shipping damage (damaged box, scratches, dents, etc.). If it is damaged or fails to meet its specifications, notify our service department or your local sales representative immediately.
2.3 Jumper Settings We designed the PCI-1753/1753E with ease-of-use in mind. It is a "plug and play" card, i.e. the system BIOS assigns the system resources such as base address and interrupt automatically. There are only two functions with 17 jumpers on the PCI-1753, and one function with 16 jumpers on the PCI-1753E. The following section describes how to configure the card. You may want to refer to the figure below for help in identifying card components.
Using Jumpers to Set Ports as Output Ports By shorting the two pins of the jumpers JPA0, JPB0, JPC0L, JPC0H, JPA1, JPB1, JPC1L, JPC1H, JPA2, JPB2, JPC2L, JPC2H, JPA3, JPB3, JPC3L or JPC3H, a user sets the corresponding ports to be output ports. (JPA0 means jumper for port A0, JPB0 means jumper for port B0, etc.) Shorting the two pins of a port's jumper disables the port from being software configurable as an input port.
Table 2-1: Summary of jumper settings Names of Jumpers Function description JPA0, JPA1, JPA2 and JPA3: Jumpers for ports A0, A1, A2 and A3 Sets port as an output port JPB0, JPB1, JPB2 and JPB3: Jumpers for ports B0, B1, B2 and B3 JPC0L, JPC1L, JPC2L and JPC3L: Jumpers for low nibble of ports C0, C1, C2 and C3 Sets port to be software configurable as input or output (default) JPC0H, JPC1H, JPC2H and JPC3H: Jumpers for high nibble of ports C0, C1, C2 and C3 1 Enables the reset protection function.
2.4 Installation Instructions The PCI-1753/1753E can be installed in any PCI slot in the computer. However, refer to the computer user's manual to avoid any mistakes and danger before you follow the installation procedure below: 1. Turn off your computer and any accessories connected to the computer. Warning!: TURN OFF your computer power supply whenever you install or remove any card, or connect and disconnect cables. 2. Disconnect the power cord and any other cables from the back of the computer. 3.
6. Secure the PCI-1753/1753E card by screwing the mounting bracket to the back panel of computer. 7. Attach any accessories (100-pin cable, wiring terminal board, etc.) to the card. 8. Replace the cover of your computer. Connect the cables you removed in step 2. 9. Turn the computer power on.
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CHAPTER 3 Operation Chapter 3 Function Description 17
3.1 Overview This chapter describes the operating characteristics of the PCI-1753/ 1753E. The driver software bundled with this card allows a user to access all of the card's functions without register level programming. Please see the User's Manual included on the driver CD-ROM for more information. For users who prefer to implement their own bitlevel programming to drive the card's functions, information useful for making such a program is included in this chapter. 3.2 Digital I/O Ports 3.2.
3.2.3 Input/Output Control A control word can be written to a port's configuration register (Base+3, 7, 11 and 15 respectively for ports 0, 1, 2 and 3 on the PCI1753, and Base+35, 39, 43 and 47 respectively for ports 0, 1, 2 and 3 on the PCI-1753E) to set the port as an input or an output port, unless the ports are set as output ports via jumpers (refer to Section 2.3, Jumper Settings). Table 3-1 shows the format of a control word.
If the jumper JP1 is enabled and the initial configuration is caused by a reset, all ports will return to the states they had just prior to the reset. The reset must be a "hot" reset (power not disconnected) for enabled JP1 to return ports to their prior values. Otherwise, the card behaves as though JP1 were not enabled. Please refer to "Jumper settings" in Chapter 2 for more information. 3.2.
3.3 Interrupt Functions 3.3.1 Introduction Two lines of each I/O port C, plus ports A0 and B0, are connected to the interrupt circuitry. The “Interrupt Control Register” of the PCI1753/1753E controls how the combination of these signals generates an interrupt. Six interrupt request signals can be generated at the same time, and then the software can service these six request signals by IRQ. The multiple interrupt sources provide the card with more capability and flexibility. 3.3.
Table 3-2: Interrupt control register bit map Base+16/48 Port 0 Bit # D7 D6 D5 D4 D3 D2 D1 D0 Abbreviation F0 E0 M01 M00 F02 M2 F01 M1 Bit # D7 D6 D5 D4 D3 D2 D1 D0 Abbreviation F1 E1 M11 M10 - - - - Base+17/49 Port 1 Base+18/50 Port 2 Bit # D7 D6 D5 D4 D3 D2 D1 D0 Abbreviation F2 E2 M21 M20 - - - - Base+19/51 Port 3 Bit # D7 D6 D5 D4 D3 D2 D1 D0 Abbreviation F3 E3 M31 M30 - - - - Mn0 and Mn1: “mode bits” of port Cn (n = 0 ~ 3)
M 0 1 :M 0 0 PC00 PC04 0 0 0 1 1 0 1 1 M 11 :M 1 0 0 0 PC10 PC14 0 1 1 0 1 1 VCC M 2 1 :M 2 0 0 0 PC20 PC24 0 1 1 0 1 1 PC34 0 1 1 0 1 1 Q CLK M 3 1 :M 3 0 0 0 PC30 D IN T # A M1 0 P attern m atch (PA 0 ) 1 M2 0 S tate ch an g e (P B 0) 1 Figure 3-2: Interrupt sources Chapter 3 Function Description 23
3.3.4 Interrupt Source Control The “mode bits” in the interrupt control registers determine the allowable sources of signals generating an interrupt. For the PCI1753, bit 4 and bit 5 of Base+16 determines the interrupt source of port C0, bit 4 and bit 5 of Base+17 determines the interrupt source for port C1, and so forth. Because of sharing the same PCI controller with the PCI-1753, the PCI-1753E’s interrupt sources are also controlled by the PCI-1753’s interrupt control register.
3.3.5 Interrupt Triggering Edge Control The interrupt can be triggered by a rising edge or a falling edge of the interrupt signal, selectable by the value written in the “triggering edge control” bit in the interrupt control register, as shown in following table. Table 3-4: Triggering edge control bit values En (n = 0 ~ 3) Triggering edge of interrupt signal 1 Rising edge trigger 0 Falling edge trigger 3.3.
3.3.7 Pattern Match Interrupt Function The PCI-1753/1753E provides the pattern match interrupt function for port A0. It monitors the status of the enabled input channels, which are chosen in Base+24 (or Base+56 for the PCI-1753E), and compares the received state values with the pre-set state values written in Base+20 (Base+52 for the PCI-1753E). When the actual state values match the pre-set state values, the PCI-1753 will deliver an interrupt signal to the system.
c) Finally, enable the pattern match function for port A0 of the PCI1753 by writing a “1” in bit 0 of Base+16. M1 Description 1 Enable the pattern match interrupt function for port A0 0 Disable the pattern match interrupt function for port A0 d) When the input signals at channels PA01, PA02 and PA07 are high and PA06 is low, an interrupt signal will be generated. This result is not affected by the states of channels PA00, PA03, PA04 and PA05. 3.3.
b) Then, enable the change of state interrupt function for port B0 of the PCI-1753E by writing a “1” in bit 2 of Base+48. M2 Description 1 Enable the change of state interrupt function for port A0 0 Disable the change of state interrupt function for port A0 c) When a change of state occurs in PB01 or PB02 or PB06 or PB07 on the PCI-1753E, an interrupt signal is generated.
APPENDIX A Register Format of PCI-1753/1753E Appendix A Calibration 29
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APPENDIX B Pin Assignments of Cable PCL-10268 Appendix A Calibration 33
CON1 CON0 PIN PIN PIN PIN PIN PIN PIN PIN PIN PIN PIN PIN PIN PIN PIN PIN PIN PIN PIN PIN PIN PIN PIN PIN PIN PIN PIN PIN PIN PIN PIN PIN PIN PIN PIN PIN PIN PIN PIN PIN PIN PIN PIN PIN PIN PIN PIN PIN PIN PIN 01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 5
