User manual

31 Appendix A
A.2 PCI-1753E Register Format
Base
Address
+
(Decimal)
Function
Read Write
32 Port A0 Port A0
33 Port B0 Port B0
34 Port C0 Port C0
35 - Port 0 Configuration Register
36 Port A1 Port A1
37 Port B1 Port B1
38 Port C1 Port C1
39 - Port 1 Configuration Register
40 Port A2 Port A2
41 Port B2 Port B2
42 Port C2 Port C2
43 - Port 2 Configuration Register
44 Port A3 Port A3
45 Port B3 Port B3
46 Port C3 Port C3
47 - Port 3 Configuration Register
48 Interrupt Control Register for Port 0 Interrupt Control Register for Port 0
49 Interrupt Control Register for Port 1 Interrupt Control Register for Port 1
50 Interrupt Control Register for Port 2 Interrupt Control Register for Port 2
51 Interrupt Control Register for Port 3 Interrupt Control Register for Port 3
52 - Pattern Match Value Register for
Port A0
56 - Pattern Match Enable Register for
Port A0
60 - Change of State Enable Register
for Port B0