PCI-1751U 48-bit Digital Input/Output Card with Universal PCI Bus User Manual
Copyright This documentation and the software included with this product are copyrighted 2004 by Advantech Co., Ltd. All rights are reserved. Advantech Co., Ltd. reserves the right to make improvements in the products described in this manual at any time without notice. No part of this manual may be reproduced, copied, translated or transmitted in any form or by any means without the prior written permission of Advantech Co., Ltd. Information provided in this manual is intended to be accurate and reliable.
Contents Chapter 1 General Information ....................................... 2 1.1 Chapter Introduction ....................................................................... 2 1.1.1 1.1.2 1.1.3 1.1.4 1.1.5 1.1.6 1.1.7 1.1.8 2 Installation ....................................................... 6 2.1 2.2 2.3 Initial Inspection................................................................ 6 Unpacking ......................................................................... 6 Jumper Settings .......
3.3.3 3.3.4 3.4 Counter 2 ...................................................................... 20 Timer/Counter Frequency and Interrupt ...................... 20 Interrupt Function............................................................ 21 3.4.1 3.4.2 3.4.3 3.4.4 3.4.5 3.4.6 Introduction .................................................................. 21 IRQ Level .................................................................... 21 Interrupt Control Register (Base + 32) .....................
1 CHAPTER 2 General Information
Chapter 1 General Information 1.1 Introduction The PCI-1751U is a 48-bit DI/O and counter/timer card with Universal PCI bus. It provides you with 48 bits of parallel digital input/output as well as 3 timers. It emulates mode 0 of the 8255 PPI chip, but the buffered circuits offer a higher driving capability than the 8255. The card emulates two 8255 PPI chips to provide 48 DI/O bits. The I/O bits are divided into six 8-bit I/O ports: A0, B0, C0, A1, B1 and C1.
• High density SCSI 68-pin connector • Output status readback • Two 16-bit timers can be cascaded to one 32-bit timer, and can generate watchdog timer interrupts • One 16-bit event counter can generate event interrupts • Keeps port I/O settings and digital output states after hot system reset • Supports dry contact and wet contact • BoardID 1.1.
1.1.7 Interrupt Source • PC00, PC04, PC10, PC14, Timer 1 and Counter 2. 1.1.8 Transfer Rate (This value depends on software and speed of computer.) • Typical: 1 MB/sec (tested under DOS, Pentium® 100 MHz CPU) • Maximum: 1.5 MB/sec • Connector: One SCSI-II 68-pin female connector • Power consumption: 5 V @ 850 mA (Typical) 5 V @ 1.0 A (Max.
CHAPTER 2 2 Installation
Chapter 2 Installation 2.1 Initial Inspection Before starting to install the PCI-1751U, make sure there is no visible damage on the card. We carefully inspected the card both mechanically and electrically before shipment. It should be free of marks and in perfect order on receipt. As you unpack the PCI-1751U, check it for signs of shipping damage (damaged box, scratches, dents, etc.
2.3 Jumper Settings We designed the PCI-1751U with ease-of-use in mind. It is a "plug and play" card, i.e. the system BIOS assigns the system resources such as base address and interrupt automatically. There are only two functions with 11 jumpers to be set by the user. The following section describes how to configure the card. You may want to refer to the figure below for help in identifying card components. Figure 2.1: Location of Connectors and Jumpers 2.3.
2.3.2 Using Jumpers to Set Ports as Output Ports By shorting the lower two pins of the jumpers JPA0, JPB0, JPC0L, JPC0H, JPA1, JPB1, JPC1L or JPC1H, a user sets the corresponding ports to be output ports. (JPA0 means jumper for port A0, JPB0 means jumper for port B0, etc.) Shorting the lower two pins of a port's jumper pins disables the port from being software configurable as an input port.
2.3.4 Select Clock Source of Timers and Counter Jumpers JP1, JP2 and JP3 are used to select the clock source of Timer 0, Timer 1 and Counter 2, respectively. Short the upper two pins of the jumpers to select an external clock source, or short the lower two pins to select an internal clock source. However, the internal clock source of Timer 1 is connected to the output of Timer 0, so shorting the upper two pins of JP2 results in the cascading of Timer 0 and Timer 1 as a 32-bit timer. Table 2.
2.4 Setting the BoardID Switch (SW1) You can use the BoardID command (0x20) to get the board’s unique identifier. PCI-1751U has a built-in BoardID DIP switch (SW1), which is used to define each card's unique identifier. You can determine the identifier in the register as shown in Table 2.2. When there are multiple cards on the same chassis, this BoardID setting is useful for identifying each card's device number. We set the PCI-1751U’s BoardID switch to 0 at the factory.
2.5 PCI-1751U Block Diagram Figure 2.
2.6 Pin Assignments Port0: PA00 ~ PA07: I/O pins of Port A0 PB00 ~ PB07: I/O pins of Port B0 PC00 ~ PC07: I/O pins of Port C0 Port1: PA10 ~ PA17: I/O pins of Port A1 PB10 ~ PB17: I/O pins of Port B1 PC10 ~ PC17: I/O pins of Port C1 CNT0_OUT, CNT1_OUT and CNT2_OUT: Output pins of Counter/Timer 0, 1 and 2 CNT0_CLK, CNT1_CLK and CNT2_CLK: External clock source of Counter / Timer 0, 1 and 2 CNT0_G, CNT1_G and CNT2_G: Gate control pins of Counter / Timer 0, 1 and 2 INT_OUT: Interrupt output.
2.7 Installation Instructions The PCI-1751U can be installed in any PCI slot in the computer. However, refer to the computer user's manual to avoid any mistakes and danger before you follow the installation procedure below: 1. Turn off your computer and any accessories connected to the computer. Warning! TURN OFF your computer power supply whenever you install or remove any card, or connect and disconnect cables. 2. Disconnect the power cord and any other cables from the back of the computer. 3.
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CHAPTER 3 2 Operation
Chapter 3 Installation 3.1 Operation This chapter describes the operating characteristics of the PCI-1751U. The driver software provided allows a user to access all of the card's functions without register level programming. Please see the User's Manual for the driver bundled with this card for more information. For users who prefer to implement their own bit-level programming to drive the card's functions, information useful for making such a program is included in this chapter. 3.2 Digital I/O Ports 3.2.
3.2.3 Interrupt Function of the DIO Signals Two I/O pins (PC00 and PC10) can be used to generate hardware interrupts. A user can program the interrupt control register (Base + 32) to select the interrupt sources. Refer to "Interrupt Function" in this chapter for details about interrupt control. 3.2.
If the jumper JA1 is enabled and the initial configuration is caused by a reset, all ports will return to the states they had just prior to the reset. The reset must be a "hot" reset (power not disconnected) for enabled JA1 to return ports to their prior values. Otherwise, the card behaves as though JA1 were not enabled. Refer to "Jumper settings" in Chapter 2 for more information. 3.2.
3.3 Timer/Counter Operation 3.3.1 Introduction The PCI-1751U includes one 8254 compatible programmable timer/ counter chip which provides three 16-bit counters, designated as Timer 0, Timer1 and Counter 2. Each has 6 operation modes. Timer 0 and Timer 1 can be used separately or can be cascaded to create one 32-bit timer. Both Timer 1 and Counter 2 can generate interrupts to the computer. Please refer to Appendix A for more information on the operation modes of the counter chip.
Setting jumper JP1 sets the clock source of Timer 0 to be external, and this allows Timer 0 and Timer 1 to be cascaded into a 32-bit event counter. 3.3.3 Counter 2 Counter 2 can be a 16-bit timer or an event counter, selectable by setting JP3. When the clock source is set for an internal source, Counter 2 is a 16-bit timer; when set as an external source, then Counter 2 is an event counter. Counter 2 is set as mode 0 (interrupt on terminal count) in the driver provided by Advantech. 3.3.
3.4 Interrupt Function 3.4.1 Introduction Two lines in each I/O port (C0 and C4) and two of the three counter outputs (Timer 1 and Counter 2) are connected to the interrupt circuitry. The "Interrupt Control Register" of the PCI-1751U controls how the combination of the 6 signals generates an interrupt. Two interrupt request signals can be generated at the same time, and then the software can service these two request signals by ISR.
3.4.4 Interrupt Source Control The "mode bits" in the interrupt control register determine the allowable sources of signals generating an interrupt. Bit 0 and bit 1 determine the interrupt source for port 0, and bit 4 and bit 5 determine the interrupt source for port 1, as indicated in Figure 3-3. Table 3-3 shows the relationship between an interrupt source and the values in the mode bits. Figure 3.3: Figure 3-3: Interrupt sources Table 3.
3.4.5 Interrupt Triggering Edge Control The interrupt can be triggered by a rising edge or a falling edge of the interrupt signal, selectable by the value written in the "triggering edge control" bit in the interrupt control register, as shown in Table 3-4. Table 3.4: Triggering edge control bit values E0 or E1 Triggering edge of interrupt signal 1 Rising edge trigger 0 Falling edge trigge 3.4.6 Interrupt Flag Bit The "interrupt flag" bit is a flag indicating the status of an interrupt.
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A APPENDIX 2 Function of 8254 Counter Chip
Appendix A Function of 8254 Counter Chip A.1 The Intel 8254 The PCI-1751U uses the Intel 8254 compatible programmable interval timer/counter. The popular 8254 offers three independent 16-bit down counters. Each counter has a clock input, control gate and an output. You can program each counter for maximum count values from 2 to 65535. The 8254 has a maximum input clock frequency of 10 MHz. The PCI1751U provides 10 MHz input frequencies to the counter chip from an on-board crystal oscillator.
The data format for the control register appears below: BASE+27 8254 control, standard mode Bit D7 D6 D5 D4 D3 D2 D1 D0 Value SC1 SC0 RW1 RW0 M2 M1 M0 BCD Description: SC1 & SC0Select counter Counter SC1 SC0 0 0 0 1 0 1 2 1 0 Read-back command 1 1 RW1 & RW0Select read/write operation Operation RW1 RW0 Counter latch 0 0 Read/write LSB 0 1 Read/write MSB 1 0 Read/write LSB first, 1 1 then MSB M2, M1 & M0Select operating mode M2 M1 M0 Mode 0 0 0 0 programm
BCD Select binary or BCD counting BCD Type 0 Binary counting 16-bits 1 Binary coded decimal (BCD) counting If you set the module for binary counting, the count can be any number from 0 up to 65535. If you set it for BCD (Binary Coded Decimal) counting, the count can be any number from 0 to 9999. If you set both SC1 and SC0 bits to 1, the counter control register is in read-back command mode.
A.3 Counter Operating Modes A.3.1 MODE 0 – Stop on Terminal Count The output will be initially low after you set this mode of operation. After you load the count into the selected count register, the output will remain low and the counter will count. When the counter reaches the terminal count, its output will go high and remain high until you reload it with the mode or a new count value. The counter continues to decrement after it reaches the terminal count.
A.3.4 MODE 3 – Square Wave Generator This mode is similar to Mode 2, except that the output will remain high until one half of the count has been completed (for even numbers), and will go low for the other half of the count. This is accomplished by decreasing the counter by two on the falling edge of each clock pulse. When the counter reaches the terminal count, the state of the output is changed, the counter is reloaded with the full count and the whole process is repeated.
A.4 Counter Operations A.4.1 Read/Write Operation Before you write the initial count to each counter, you must first specify the read/write operation type, operating mode and counter type in the control byte and write the control byte to the control register (BASE+27). Since the control byte register and all three counter read/write registers have separate addresses and each control byte specifies the counter it applies to (by SC1 and SC0), no instructions on the operating sequence are required.
counters at the same time. A subsequent read operation on the selected counter will retrieve the latched value. A.5 Counter Applications The 8254 compatible programmable interval timer/counter on your PCI1751U interface card is a a very useful device. You can program timers 1 and 2 to serve as timers, event counters, square wave generators, or as a watchdog to generate regular interrupts at a fixed interval.
B APPENDIX 2 Register Format of PCI-1751U
Appendix B Register Format of PCI1751U Base Address + (Decimal) Function Read Write 0 Port A0 Port A0 1 Port B0 Port B0 2 Port C0 Port C0 3 Port 0 Configuration Register 4 Port A1 Port A1 5 Port B1 Port B1 6 Port C1 Port C1 7 Port 1 Configuration Register 8 ~ 19 Reserved Reserved 20 BoardID Reserved 21~23 Reserved Reserved 24 8254 Counter 0 8254 Counter 0 25 8254 Counter 1 8254 Counter 1 26 8254 Counter 2 8254 Counter 2 28 Reserved Reserved 29 Reserved Reserve
