Specifications
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INSN_CONFIG_8254_READ_STATUS. Reads the status register value for the
counter channel into data[1].
INSN_CONFIG_SET_CLOCK_SRC. Sets the counter channel’s clock source as
specified in data[1] (this is a hardware-specific value). Not
supported on PC214E. For the other boards, valid clock sources are
0 to 7 as follows:
0. CLK n, the counter channel’s dedicated CLK input from the SK1
connector. (N.B. for other values, the counter channel’s CLKn
pin on the SK1 connector is an output!)
1. Internal 10 MHz clock.
2. Internal 1 MHz clock.
3. Internal 100 kHz clock.
4. Internal 10 kHz clock.
5. Internal 1 kHz clock.
6. OUT n-1, the output of counter channel n-1 (see note 1 below).
7. Ext Clock, the counter chip’s dedicated Ext Clock input from
the SK1 connector. This pin is shared by all three counter
channels on the chip.
INSN_CONFIG_GET_CLOCK_SRC. Returns the counter channel’s current
clock source in data[1]. For internal clock sources, data[2] is set
to the period in ns.
INSN_CONFIG_SET_GATE_SRC. Sets the counter channel’s gate source as
specified in data[2] (this is a hardware-specific value). Not
supported on PC214E. For the other boards, valid gate sources are 0
to 7 as follows:
0. VCC (internal +5V d.c.), i.e. gate permanently enabled.
1. GND (internal 0V d.c.), i.e. gate permanently disabled.
2. GAT n, the counter channel’s dedicated GAT input from the SK1
connector. (N.B. for other values, the counter channel’s GATn
pin on the SK1 connector is an output!)
3. /OUT n-2, the inverted output of counter channel n-2 (see note
2 below).
4. Reserved.
5. Reserved.
6. Reserved.
7. Reserved.
INSN_CONFIG_GET_GATE_SRC. Returns the counter channel’s current gate
source in data[2].
Clock and gate interconnection notes:
1. Clock source OUT n-1 is the output of the preceding channel on the
same counter subdevice if n > 0, or the output of channel 2 on the
preceding counter subdevice (see note 3) if n = 0.
2. Gate source /OUT n-2 is the inverted output of channel 0 on the
same counter subdevice if n = 2, or the inverted output of channel n+1
on the preceding counter subdevice (see note 3) if n < 2.
3. The counter subdevices are connected in a ring, so the highest
counter subdevice precedes the lowest.
The ’INTERRUPT’ subdevice pretends to be a digital input subdevice. The
digital inputs come from the interrupt status register. The number of
channels matches the number of interrupt sources. The PC214E does not