Copyright This documentation and the software included with this product are copyrighted 1999 by Advantech Co., Ltd. All rights are reserved. Advantech Co., Ltd. reserves the right to make improvements in the products described in this manual at any time without notice. No part of this manual may be reproduced, copied, translated or transmitted in any form or by any means without the prior written permission of Advantech Co., Ltd. Information provided in this manual is intended to be accurate and reliable.
Contents 1. Introduction .................................................. 1 1.1 Features ............................................................................... 1 1.2 Installation Guide ................................................................ 3 1.3 Software ............................................................................... 5 1.4 Accessories .......................................................................... 5 2. Installation ............................................
Appendix B Block Diagram ................................................ 35 Appendix C Register Structure and Format .................... 37 C.1 Overview ............................................................................ 37 C.2 I/O Port Address Map ........................................................ 37 C.3 Channel Number and A/D Data — BASE+0 and BASE+1 .............................................................................. 42 C.4 Software A/D Trigger — BASE+0 ........................
1 Chapter 1 Chapter 1. Introduction Thank you for buying the Advantech PCI-1711/1731 PCI card. The Advantech PCI-1711/1731 is a powerful data acquisition (DAS) card for the PCI bus. It features a unique circuit design and complete functions for data acquisition and control.
Chapter 1 according to their needs for the corresponding range of input voltage. The gain value settings thus selected is stored in the SRAM. This flexible design enables multi-channel and high-speed sampling for high-performance data acquisition (up to 100 KS/s .) On-board FIFO(First-In-First-Out) Memory The PCI-1711/1731 provides an on-board FIFO memory buffer, storing up 1 to 1K A/D samples. Users can either enable or disable the interrupt request feature of the FIFO buffer.
Chapter 1 1.
Chapter 1 Insta ll D river C D -R O M , the n p ow e r-off P C P lug -in H ardw a re and po w er-on P C U se con fig uration utility to con figu re ha rdw are U se testing utility to test ha rdw are R e ad e xa m ples & driver m anu al S tart to w rite your a pplication Fig. 1-1 Installation Flow Chart PCI-1711/1731 User’s Manual –4– Advantech Co., Ltd. www.advantech.
Chapter 1 1.3 Software Advantech offers a rich set of DLL drivers, third-party driver support and application software to help fully exploit the functions of your PCI-1711/1731 card: l DLL driver (on the companion CD-ROM) l Labview driver l Advantech ActiveDAQ l Advantech GeniDAQ For more information on software, please refer to Chapter 4, Software Overview. Users who intend to program directly at the registers of the DAS device can have register-level programming as an option.
Chapter 1 qPCLD-8710 The PCLD-8710 is a DIN-rail mounting screwterminal board to be used with any of the PC-LabCards which have 68-pin SCSI connectors. The PCLD-8710 features the following functions: l 2 additional 20-pin flat-cable connectors for digital input and output l Reserved space on the board to meet future needs for signalconditioning circuits (low-pass filter, voltage attenuator and current shunt) l Industrial-grade screw-clamp terminal blocks for heavy-duty and reliable connections.
2 Chapter 1 Chapter 2. Installation This chapter gives users a package item checklist, proper instructions about unpacking and step-by-step procedures for both driver and card installation. 2.1 Unpacking After receiving your PCI-1711/1731 package, please inspect its contents first.
Chapter 2 Note: ✎ Keep the antistatic bag for future use. You might need the original bag to store the card if you have to remove the card from PC or transport it elsewhere. 2.2 Driver Installation We recommend you to install the driver before you install the PCI1711/1731 card into your system, since this will guarantee a smooth installation process. The 32-bit DLL driver Setup program for the PCI-1711/1731 card is included on the companion CD-ROM that is shipped with your DAS card package.
Chapter 2 Step 3: Select the DLL Drivers option. Step 4: Select the Windows 95/98 or Windows NT option according to your operating system. Just follow the installation instructions step by step to complete your DLL driver setup. Fig. 2-2 Different options for Driver Setup For further information on driver-related issues, an online version of DLL Drivers Manual is available by accessing the following path: Start/Programs/Advantech Driver for 95 and 98 (or for NT)/Driver Manual 2.
Chapter 2 Step 4: Touch the metal part on the surface of your computer to neutralize the static electricity that might be on your body. Step 5: Insert the PCI-1711/1731 card into a PCI slot. Hold the card only by its edges and carefully align it with the slot. Insert the card firmly into place. Use of excessive force must be avoided, otherwise the card might be damaged. Step 6: Fasten the bracket of the PCI card on the back panel rail of the computer with screws.
Chapter 2 Fig. 2-3 The device name listed on the Device Manager Note: ✎ If your card is properly installed, you should see the device name of your card listed on the Device Manager tab. If you do see your device name listed on it but marked with an exclamation sign “!” (Fig. 2-4), it means your card has not been correctly installed. In this case, remove the card device from the Device Manager by selecting its device name and press the Remove button. Then go through the driver installation process again.
Chapter 2 After your card is properly installed on your system, you can now configure your device using the Device Installation Program that has itself already been installed on your system during driver setup. A complete device installation procedure should include device setup, configuration and testing. The following sections will guide you through the Setup, Configuration and Testing of your device. 2.
Chapter 2 Fig. 2-6 The I/O Device Installation dialog box Step 3: Click the Add>> button and a List of Devices box will appear right below the original Installed Devices box (Fig. 2-7). Fig. 2-7 Selecting the device you want to install Step 4: Scroll down the List of Devices box to find the device that you wish to install, then click the Install button to evoke the Device(s) Found dialog box such as one shown in Fig. 2-8. The Device(s) Found dialog box lists all the installed devices on your system.
Chapter 2 Fig. 2-8 The “Device(s) Found” dialog box Configuring the Device Step 5: On the Device Setting dialog box (Fig. 2-9), you can configure the voltage source either as External or Internal, and specify the voltage output range for the 2 D/A channels. Fig. 2-9 The Device Setting dialog box Note: ✎Users can configure the source of D/A reference voltage either as Internal or External, and select the output voltage range.
Chapter 2 Step 6: After you have finished configuring the device, click OK and the device name will appear in the Installed Devices box as seen below: Fig. 2-10 The Device Name appearing on the list of devices box Note: ✎ As we have noted, the device name “000:PCI-1711 I/O=6500H” begins with a device number “000”, which is specifically assigned to each card cifically. The device number is passed to the driver to specify which device you wish to control.
Chapter 2 On the Device Test dialog box, users are free to test various functions of PCI-1711/1731 on the Analog input, Analog output, Digital input, Digital output or Counter tabs. Note: ✎You can access the Device Test dialog box either by the previous procedure for the Device Installation Program or simply by accessing Start/Programs/Advantech Driver for 95 and 98 (or for NT) /Test Utility. Testing Analog Input Function Click the Analog Input tab to bring it up to front of the screen.
Chapter 2 Fig. 2-13 Analog Output tab on the Device Test dialog box Testing Digital Input Function Click the Digital Input tab to show forth the Digital Input test panel as seen below. Through the color of the lamps, users can easily discern whether the status of each digital input channel is either high or low. Fig. 2-14 Digital Input tab on the Device Test dialog box Testing Digital Output Function Click the Digital Output tab to bring up the Digital Output test panel such as seen on the next page.
Chapter 2 Fig. 2-15 Digital Output tab on the Device Test dialog box Testing Counter Function Click the Counter Tab to bring its test panel forth. The counter channel (Channel 0) offers the users two options: Event counting and Pulse out. If you select Event counting, you need first to connect your clock source to pin CNT0_CLK, and the counter will start counting after the pin CNT0_GATE is triggered. If you select Pulse Out, the clock source will be output to pin CNT0_OUT.
3 Chapter 3 Chapter 3. Signal Connections 3.1 Overview Maintaining signal connections is one of the most important factors in ensuring that your application system is sending and receiving data correctly. A good signal connection can avoid unnecessary and costly damage to your PC and other hardware devices. This chapter provides useful information about how to connect input and output signals to the PCI-1711/1731 via the I/O connector. 3.
Chapter 3 A I0 A I2 A I4 A I6 A I8 A I1 0 A I1 2 A I1 4 A IG N D *D A 0 _ R E F * D A0_O U T * AOGND D I0 D I2 D I4 D I6 D I8 D I1 0 D I1 2 D I1 4 DGND DO0 DO2 DO4 DO6 DO8 D O 10 D O 12 D O 14 DGND C N T0_C LK C N T0_O U T C N T 0 _ G AT E +12V 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 A I1 A I3 A I5 A I7 A I9 A I11 A I1 3 A I1 5 A IG N D D A1_R EF * D
Chapter 3 I/O Connector Signal Description Signal Name Reference Direction AI<0…15> AIGND Input AIGND - - DA0_REF DA1_REF AOGND Input DA0_OUT DA1_OUT AOGND Output AOGND - - Description Analog Input Channels 0 through 15. Analog Input Ground. Analog Output Channel 0/1 External Reference. Analog Output Channels 0/1. Analog Output Ground. The analog output voltages are referenced to these nodes. DI<0..15> DGND Input DO<0..15> DGND Output Digital Input channels.
Chapter 3 3.3 Analog Input Connections The PCI-1711/1731 supports 16 single-ended analog inputs. Each individual input channel is software-selected. Single-ended Channel Connections The single-ended input configuration has only one signal wire for each channel, and the measured voltage (Vm) is the voltage of the wire as referenced against the common ground. A signal source without a local ground is also called a “floating source”.
Chapter 3 +7 V D/A output. Figure 3-3 shows how to make analog output and external reference input connections on the PCI-1711. Internal -5V -10V External DA0_REF INT_REF DA0 + DA0_OUT Load _ Load _ External Reference For DA Signal 0 AOGND DATA BUS DA1 DA1_OUT + External Reference For DA Signal 1 DA1_REF INT_REF I/O Connector Fig. 3-3 Analog output connections 3.
Chapter 3 PCI-1711/1731. When DGND is connected to TRG_GATE, the external trigger function is thereby disabled. 3.6 Field Wiring Considerations When you use the PCI-1711/1731 to acquire data from outside, noises in the environment might significantly affect the accuracy of your measurements if due cautions are not taken. The following measures will be helpful to reduce possible interference running signal wires between signal sources and the PCI-1711/1731.
4 Chapter 2 Chapter 4. Software Overview This chapter gives you an overview of the software programming choices available and a quick reference to examples of source codes that can help you be better oriented to programming. After following the instructions given in Chapter 2, it is hoped that you feel comfortable enough to proceed further. Advantech offers users several options for programming DAS cards.
Chapter 4 driver for Windows 95/98/NT works seamlessly with development tools such as Visual C++, Visual Basic, Inprise C++ Builder and Inprise Delphi. Advantech ActiveDAQ ActiveDAQ provides a collection of add-on ActiveX controls and function library to perform all data acquisition functions. It features an icon-based graphical programming interface, a VBA-compatible scripting language, and an Excel-like report generator.
Chapter 4 4.2 DLL Driver Programming Roadmap This section will provide you a roadmap to demonstrate how to build an application from scratch using Advantech DLL driver with your favorite development tools such as Visual C++, Visual Basic, Delphi and C++ Builder. The step-by-step instructions on how to build your own applications using each development tool will be given in the DLL Drivers Manual. Moreover, a rich set of example source codes are also given for your reference.
Chapter 4 Programming with DLL Driver Function Library Advanech DLL driver offers a rich function library to be utilized in various application programs. This function library consists of numerous APIs that support many development tools, such as Visual C++, Visual Basic, Delphi and C++ Builder.
5 Chapter 5 Chapter 5. Calibration This chapter offers you a brief guide to the calibration programs. Regular calibration checks are important to maintain accuracy in data acquisition and control applications. Three calibration programs are included on the companion CD-ROM : ADCAL.EXE A/D calibration program DACAL.EXE D/A calibration program (Only for PCI-1711) SELFCAL.EXE A/D self-calibration program (Only for PCI-1711) Those calibration programs are designed only for DOS environment.
Chapter 5 V R1 V R2 Fig. 5-2 PCI-1731 VR assignment The following list shows the function of each VR : VR Function VR1 A/D bipolar offset adjustment VR2 A/D full scale (gain) adjustment VR3 D/A channel 0 full scale adjustment VR4 D/A channel 1 full scale adjustment 5.2 A/D Calibration Regular and accurate calibration procedures ensure the maximum possible accuracy. The A/D calibration program ADCAL.EXE leads you through the whole A/D offset and gain adjustment procedure.
Chapter5 of ±10V to the reference input of the D/A output channel you want to calibrate. Adjust the full scale of D/A channel 0 and 1, with VR3 and VR4 respectively. Note: ✎ Using a precision voltmeter to calibrate the D/A outputs is recommended. You can adjust VR3 and VR4 until the D/A channel 0 and 1 output voltages approach the reference voltage (at least 1LSB), but with the reverse sign. For example, if Vref is -5V, then Vout should be +5V. If Vref is -10V, Vout should be +10V. 5.
Chapter 5 PCI-1711/1731 User’s Manual – 32 – Advantech Co., Ltd. www.advantech.
APPENDIX Specifications A Analog Input Channels 16 single-ended Resolution 12-bit FIFO Size 1K samples Max. Sampling Rate 100 kHz 10 µs Conversion Time Input range and Gain List Drift (ppm/°C) Small Signal Bandwidth for PGA Gain 1 2 4 8 16 ± 10V ± 5V ± 2.5V ± 1.25V ± 0.625V 1 2 4 8 16 Zero 15 15 15 15 15 Gain Gain 25 25 25 30 40 Input Gain 1 Bandwidth 4.0 MHz 2 4 8 16 2.0 MHz 1.5 MHz 0.65MHz 0.35MHz Max.
APPENDIX A Digital Input / Output Input Channels 16 Low Input Voltage 0.8 V max. High Output Channels 2.0 V min. 16 Output Voltage Low 0.8 V max.@8.0 mA (sink) High 2.0 V min.@-0.4 mA (source). Programmable Counter / Timer Channels 1 Resolution 16-bit Compatibility TTL level Base Clock 10 MHz Base Clock Accuracy 100 ppm Max. Input Frequency Input Level H/L Input Clock 10 MHz VIH 2.0 (min.) VIL 0.8 V (max.) TPWH (high pulse width) 30 ns (min.
B APPENDIX B APPENDIX Block Diagram A d d re ss D e co d e r A ddress B us P C I C o n tro lle r P C I B us D a ta B u s IN T 1 6 -b it D ig ita l O u tp u t 1 6 -b it D ig ita l In p u t A /D & D /A S ta tu s C o n tro l L o g ic 1 2 -b it D /A O u tp u t 0 1 2 -b it D /A O u tp u t 1 C N T 0_C LK 1 K S a m p le s F IFO 1 0 M H z /10 = 1 MHz IR Q C o n tro l L o g ic COU NTER 0 C N T 0_O U T C N T 0_G ATE COU NTER 1 10 M Hz OSC 1 2 -b it A /D C o n ve rto r COU NTER 2 PAC ER _O U T
APPENDIX B PCI-1711/1731 User’s Manual – 36 – Advantech Co., Ltd. www.advantech.
C APPENDIX C APPENDIX Register Structure and Format C.1 Overview The PCI-1711/1731 is delivered with an easy-to-use 32-bit DLL driver for user programming under the Windows 95/98/NT operating system. We advise users to program the PCI-1711/1731 using the 32bit DLL driver provided by Advantech to avoid the complexity of low-level programming by register. The most important consideration in programming the PCI-1711/ 1731 at the register level is to understand the function of the card's registers.
APPENDIX C Table C-1 PCI-1711/1731 register format (Part 1) Base Address + decimal 7 6 1 CH3 CH2 CH1 CH0 AD11 0 AD7 AD6 AD5 AD4 AD3 Read 5 4 3 2 1 0 AD10 AD9 AD8 AD2 AD1 AD0 Channel Number and A/D Data N/A 3 2 N/A 5 4 Status Register 7 6 CNT0 ONE/FH IRQEN IRQ F/F F/H F/E GATE EXT PACER SW N/A 9 8 N/A 11 10 N/A 13 12 PCI-1711/1731 User’s Manual – 38 – Advantech Co., Ltd. www.advantech.
APPENDIX C Table C-1 PCI-1711/1731 register format (Part 2) Base Address + decimal Read 7 6 5 4 3 2 1 0 N/A 15 14 Digital Input 17 DI15 DI14 DI13 DI12 DI11 DI10 DI9 DI8 16 DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0 D2 D1 D0 D2 D1 D0 D2 D1 D0 Counter 0 25 24 D7 D6 D5 D4 D3 Counter 1 27 26 D7 D6 D5 D4 D3 Counter 2 29 28 D7 D6 D5 D4 D3 N/A 31 30 Advantech Co., Ltd. www.advantech.
APPENDIX C Table C-1 PCI-1711/1731 register format (Part 3) Base Address + decimal Write 7 6 5 4 3 2 1 0 G1 G0 Software A/D Trigger 1 0 A/D Channel Range Setting 3 2 G2 MUX Control 5 Stop channel 4 Start channel Control Register 7 6 CNT0 ONE/FH IRQEN GATE EXT PACER SW DA11 DA10 DA9 DA8 DA3 DA1 DA0 DA11 DA10 DA9 DA8 DA3 DA1 DA0 Clear Interrupt and FIFO 9 clear FIFO 8 clear interrupt D/A Output Channel 0 11 10 DA7 DA6 DA5 DA4 DA2 D/A Output Channel 1 13 12 DA7
APPENDIX C Table C-1 PCI-1711/1731 register format (Part 4) Base Address + decimal Write 7 6 5 4 3 2 1 0 DA1_5/10 DA0_I/E DA0_5/10 D/A Reference Control 15 14 DA1_I/E Digital Output 17 DO15 DO14 DO13 DO12 DO11 DO10 DO9 DO8 16 DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0 D2 D1 D0 D2 D1 D0 D2 D1 D0 D2 D1 D0 Counter 0 25 24 D7 D6 D5 D4 D3 Counter 1 27 26 D7 D6 D5 D4 D3 Counter 2 29 28 D7 D6 D5 D4 D3 Counter Control 31 30 D7 Advantech Co., Ltd. www.advantech.
APPENDIX C C.3 Channel Number and A/D Data — BASE+0 and BASE+1 BASE+0 and BASE+1 hold the result of A/D conversion data. The 12 bits of data from the A/D conversion are stored in BASE+1 bit 3 to bit 0 and BASE+0 bit 7 to bit 0.BASE+1 bit 7 to bit 4 hold the source A/D channel number.
APPENDIX C C.5 A/D Channel Range Setting — BASE+2 Each A/D channel has its own input range, controlled by a gain code stored in the on-board RAM. To change the range code for a channel: l Write the same channel in BASE+4 (the start channel) and BASE+5 (the stop channel) (refer to Section C.6). l write the gain code to BASE+2 bit 0 to bit 2.
APPENDIX C C.6 MUX Control — BASE+4 and BASE+5 Table C-5 Register for multiplexer control Write Bit # MUX Control 7 6 5 4 3 2 1 0 BASE+5 CH3 CH2 CH1 CH0 BASE+4 CL3 CL2 CL1 CL0 CL3 ~ CL0 Start Scan Channel Number CH3 ~ CH0 Stop Scan Channel Number l When you set the gain code of analog input channel n, you should set the MUX start&stop channel number to channel n to prevent any unexpected errors.
APPENDIX C Example 2 If the start scan channel is AI13 and the stop scan channel is AI2, then the scan sequence is AI13, AI14, AI15, AI0, AI1, AI2, AI13, AI14, AI15, AI0, AI1, AI2, AI13, AI14… C.7 Status Register — BASE+6 and BASE+7 The registers of BASE+6 and BASE+7 provide information for A/D configuration and operation.
APPENDIX C C.8 Control Register — BASE+6 The write-only register BASE+6 allows users to set an A/D trigger source and an interrupt source. Table Control Register Read Bit # Status Register 7 6 5 4 BASE+7 BASE+6 SW PACER EXT CNT0 ONE/FH IRQEN 3 2 1 0 IRQ F/F F/H F/E GATE EXT PACER SW Software trigger enable bit 1 enable; 0 disable. Pacer trigger enable bit 1 enable; 0 disable. External trigger enable bit 1 enable; 0 disable. Note! ✎ Users cannot enable SW, PACER and EXT concurrently.
APPENDIX C C.9 Clear Interrupt and FIFO — BASE+8 and BASE+9 Writing data to either of these two bytes clears the interrupt or the FIFO. Table C-8 Register to clear interrupt and FIFO Write Clear Interrupt and FIFO Bit # 7 6 5 4 3 BASE+9 Clear FIFO BASE+8 Clear Interrupt 2 1 0 C.10 D/A Output Channel 0 — BASE+10 and BASE+11 The write-only registers of BASE+10 and BASE+11 accept data for D/A Channel 0 output. PCI-1731 The PCI-1731 is not equipped with the D/A functions.
APPENDIX C C.11 D/A Output Channel 1 — BASE+12 and BASE+13 The write-only registers of BASE+12 and BASE+13 accept data for D/A channel 1 output. PCI-1731 The PCI-1731 is not equipped with the D/A functions.
APPENDIX C C.12 D/A Reference Control —BASE+14 The write-only register of BASE+14 allows users to set the D/A reference source. PCI-1731 The PCI-1731 is not equipped with the D/A functions. PCI-1711 Table C-11 Register for D/A reference control Write Bit # D/A Reference Control 7 6 5 4 3 2 1 0 DA1_I/E DA1_5/10 DA0_I/E DA0_5/10 BASE+15 BASE+14 DA0_5/10 DA0_I/E DA1_5/10 DA1_I/E Advantech Co., Ltd. www.advantech.
APPENDIX C C.13 Digital I/O Registers — BASE+16 and BASE+17 The PCI-1711/1731 offers 16 digital input channels and 16 digital output channels. These I/O channels use the input and output ports at addresses BASE+16 and BASE+17.
D APPENDIX D APPENDIX 82C54 Counter Function D.1 The Intel 82C54 The PCI-1711/1731 uses one Intel 82C54 compatible programmable interval timer/counter chip. The popular 82C54 offers three independent 16-bit counters, counter 0, counter 1 and counter 2. Each counter has a clock input, control gate and an output. You can program each counter for maximum count values from 2 to 65535. The 82C54 has a maximum input clock frequency of 10 MHz.
APPENDIX D Since the 82C54 counter uses a 16-bit structure, each section of read/write data is split into a least significant byte (LSB) and most significant byte (MSB). To avoid errors it is important that you make read/write operations in pairs and keep track of the byte order.
APPENDIX D If you set the module for binary counting, the count can be any number from 0 up to 65535. If you set it for BCD (Binary Coded Decimal) counting, the count can be any number from 0 to 9999. If you set both SC1 and SC0 bits to 1, the counter control register is in read-back command mode.
APPENDIX D 2. Writing to the second byte starts the new count. MODE 1 – Programmable One-shot Pulse The output is initially high. The output will go low on the count following the rising edge of the gate input. It will then go high on the terminal count. If you load a new count value while the output is low, the new value will not affect the duration of the one-shot pulse until the succeeding trigger. You can read the current count at any time without affecting the one-shot pulse.
APPENDIX D MODE 4 –Software-Triggered Strobe After the mode is set, the output will be high. When the count is loaded, the counter will begin counting. On terminal count, the output will go low for one input clock period then go high again. If you reload the count register during counting, the new count will be loaded on the next CLK pulse. The count will be inhibited while the GATE input is low.
APPENDIX D The read-back command can also latch status information for selected counter(s) by setting STA bit = 0. The status must be latched to be read; the status of a counter is accessed by a read from that counter. The counter status format appears at the beginning of the chapter. Counter Latch Operation Users often want to read the value of a counter without disturbing the count in progress. You do this by latching the count value for the specific counter then reading the value.
