Specifications

104
Table C-1 PCI-1710/1710L/1710HG/1710HGL/1711/1711L
register format (Part 4)
Write
Base
Address
+decimal
7 6 5 4 3 2 1 0
Software A/D Trigger
1
0
A/D Channel Range Setting
3
2 *S/D *B/U G2 G1 G0
Multiplexer Control
5 Stop channel
4 Start channel
A/D Control Register
7
6 CNT0 ONE/FH IRQEN GATE EXT0 PACER SW
Clear Interrupt and FIFO
9 Clear FIFO
8 Clear interrupt
D/A Output Channel 0
11 DA11 DA10 DA9 DA8
10 DA7 DA6 DA5 DA4 DA3 DA2 DA1 DA0
D/A Output Channel 1
13 DA11 DA10 DA9 DA8
12 DA7 DA6 DA5 DA4 DA3 DA2 DA1 DA0
D/A Control Register
15
14 DA1_I/E DA1_5/10 DA0/I/E DA0_5/10
*: S/D, B/U are not supported for PCI-1711/1711L