Specifications

92
A.3 PCI-1716/1716L Specifications
Analog Input
Channels 16 Single-Ended or 8rdiggerential or combination
Resolution 16-bit
FIFO Size 1K samples
Max. Sampling
Rate
250 KS/s max.
Conversion Time 2.5 µs
Gain 0.5 1 2 4 8
Unipolar N/A 0~10 0~5 0~2.5 0~1.2
Input range and
Gain List
Bipolar ±10V ±5V ±2.5V ±1.25V ±0.625V
Gain 0.5 1 2 4 8 Small Signal
Bandwidth for
PGA
Bandwidth
4.0 M Hz 4.0 M Hz 2.0 M Hz 1.5 M Hz
0.65 M
Hz
Common mode
Voltage
± 11 V max. ( operational )
Max. Input
Voltage
±20V
Input Protect 30 Vp-p
Input Impedance 100 MO / 10 pF(Off) ; 100 MO / 10 0pF(On)
Trigger Mode Software, On-board Programmable Pacer or external
INLE: ± 1 LSB
INLE: ± 1 LSB
Zero (Offset) error: Adjustable to ± 1 LSB
Gain 0.5 1 2 4 8
DC
Gain
error
(%FSR)
0.15 0.03 0.03 0.05 0.1
SNR : 82 dB
ENOB: 13.5 bits
Accuracy
AC
THD: - 84 Db typical
Trigger
Mode
Software, on-board programmable pacer or external
A/D
pacer
clock
250 k Hz (max.) ; 58 µs Hz (min.)
Clocking and
Trigger Inputs
External
A/D
trigger
Clock
Min. pulse width: 2µs (high); 2 µs ( low)
Max. frequency: 250kHz