Copyright Notice This documentation and the software included with this product are copyrighted 2003 by Advantech Co., Ltd. All rights are reserved. Advantech Co., Ltd. reserves the right to make improvements in the products described in this manual at any time without notice. No part of this manual may be reproduced, copied, translated or transmitted in any form or by any means without the prior written permission of Advantech Co., Ltd.
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Contents 1. Introduction···········································································································3 1.1 Features ·········································································································5 1.2 Installation Guide ························································································9 1.3 Software ······································································································11 1.
5.2 PCI-1711/1711L Calibration····································································67 5.3 PCI-1716/1716L Calibration ···································································71 Appendix A. Specifications ··················································································87 A.1 PCI-1710/1710L/1710HG/1710HGL ···················································87 A.2 PCI-1711/1711L Specifications ·····························································90 A.
C.15 Digital I/O Registers — BASE+16 and BASE+17 ·······················128 C.16 Calibration Registers — BASE+18 and BASE+19·······················129 C.17 Board ID Registers — BASE+20·····················································131 C.18 Programmable Timer/Counter Registers BASE+24, BASE+26, BASE+28 and BASE+30···············································131 Appendix D. 82C54 Counter Chip Function·················································133 D.
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Tables Table 3-1 I/O Connector Signal Description ························································40 Table C-1 PCI-1710/1710L/1710HG/1710HGL/1711/1711L register format (Part 1) ······················································································101 Table C-1 PCI-1716/1716L register format (Part 2)·········································102 Table C-1 PCI-1710/1710L/1710HG/1710HGL/1711/1711L/ 1716/1716L register format (Part 3)·················································103 Tab
Table C-14 Register for load D/A channel 1 data ·············································124 Table C-15 Register for D/A channel 1 data······················································125 Table C-16 PCI-1710/1710HG/1711 Register for D/A reference control····126 Table C-17 PCI-1716 Register for D/A reference control ······························126 Table C-18 Register for digital input··································································128 Table C-19 Register for digital output·······
Figures Fig.1-1 Installation Flow Chart ···············································································10 Fig.2-1 The Setup Screen of Advantech Automation Software ·························19 Fig.2-2 Different options for Driver Setup····························································20 Fig.2-3 The device name listed on the Device Manager····································23 Fig. 2-4 The Device Manager dialog box······························································25 Fig.
Fig. 5-4 Selecting the device you want to calibrate·············································73 Fig. 5-5 Warning message before start calibration ··············································73 Fig. 5-6 Auto A/D Calibration Dialog Box···························································74 Fig. 5-7 A/D Calibration Procedure 1····································································74 Fig.
CHAPTER 1 1 Introduction
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1. Introduction Thank you for buying the Advantech PCI-1710/1710L/1710HG/ 1710HGL/1711/1711L/1716/1716L PCI card. The Advantech PCI1710/1710L/1710HG/1710HGL/1711/1711L/1716/1716L is a powerful data acquisition (DAS) card for the PCI bus. It features a unique circuit design and complete functions for data acquisition and control, including A/D conversion, D/A conversion, digital input, digital output, and counter/timer.
w/o analog output PCI-1711 12-bit, 100kS/s 16-ch S.E. Inputs Low-cost Multifunction card PCI-1711L 12-bit, 100kS/s 16-ch S.E.
1.
Plug-and-Play Function The Advantech PCI-1710/1710L/1710HG/1710HGL/1711/1711L/ 1716/1716L is a Plug-and-Play device, which fully complies with the PCI Specification. Rev 2.1 for PCI-1710/1710L/1710HG/1710HGL/ 1711/1711L, and Rev 2.2 for PCI-1716/1716L. During card installation, all bus-related configurations such as base I/O address and interrupts are conveniently taken care of by the Plug-and-Play function. You have virtually no need to set any jumpers or DIP switches.
On-board FIFO (First-In-First-Out) Memory The PCI-1710/1710L/1710HG/1710HGL/1711/1711L/1716/1716L provides an on-board FIFO memory buffer, storing up to 4K A/D samples. Users can either enable or disable the interrupt request feature of the FIFO buffer. While the interrupt request for FIFO is enabled, users are allowed to specify whether an interrupt request will be sent with each sampling action or only when the FIFO buffer is half saturated.
On-board Programmable Counter The PCI-1710/1710L/1710HG/1710HGL/1711/1711L/1716/1716L is equipped with a programmable counter, which can serve as a pacer trigger for A/D conversions. The counter chip is an 82C54 or its equivalent, which incorporates three 16-bit counters on a 10 MHz clock. One of the three counters is used as an event counter for input channels or pulse generation. The other two are cascaded into a 32-bit timer for pacer triggering.
1.
Fig.
1.3 Software Advantech offers a rich set of DLL drivers, third-party driver support and application software to help fully exploit the functions of your PCI-1710/1710L/1710HG/1710HGL/1711/1711L/1716/1716L card: w DLL driver (on the companion CD-ROM) w LabVIEW driver w Advantech ActiveDAQ w Advantech GeniDAQ For more information on software, please refer to Chapter 4, Software Overview.
1.4 Accessories Advantech offers a complete set of accessory products to support the PCI-1710/1710L/1710HG/1710HGL/1711/1711L/1716/1716L cards. These accessories include: Wiring Cable n PCL-10168 The PCL-10168 shielded cable is specially designed for PCI-1710/1710L/1710HG/ 1710HGL/1711/1711L/1716/1716L cards to provide high resistance to noise.
n PCLD-8710 The PCLD-8710 is a DIN-rail mounting screw-terminal board to be used with any of the PC-LabCards which have 68-pin SCSI connectors. The PCLD-8710 features the following functions: w Two additional 20-pin flat-cable connectors for digital input and output w Reserved space on the board to meet future needs for signal-conditioning circuits (e.g. low-pass filter, voltage attenuator and current shunt) w Industrial-grade screw-clamp terminal blocks for heavy-duty and reliable connections.
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CHAPTER 2 Installation 15
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2. Installation This chapter gives users a package item checklist, proper instructions about unpacking and step-by-step procedures for both driver and card installation. Be noted that using PCI-1710 for example. 2.1 Unpacking After receiving your PCI-1710/1710L/1710HG/1710HGL/1711/ 1711L/1716/1716L package, please inspect its contents first.
before opening the bag. w Take hold of the card only by the metal bracket when removing it out of the bag. After taking out the card, first you should: w Inspect the card for any possible signs of external damage (loose or damaged components, etc.). If the card is visibly damaged, please notify our service department or our local sales representative immediately. Avoid installing a damaged card into your system.
2.2 Driver Installation We recommend you to install the driver before you plug the PCI-1710/1710L/1710HG/1710HGL/1711/1711L/1716/1716L card into your system, since this will guarantee a smooth installation process. The 32-bit DLL driver Setup program for the PCI-1710/1710L/ 1710HG/1710HGL/1711/1711L/1716/1716L card is included on the companion CD-ROM that is shipped with your DAS card package.
Note: If the autoplay function is not enabled on your computer, use Windows Explorer or Windows Run command to execute SETUP.EXE on the companion CD-ROM. Step 3: Select the Installation option, then the Individual Drivers option. Step 4: Select the specific device then just follow the installation instructions step by step to complete your device driver setup. Fig.
2.3 Hardware Installation Note: Make sure you have installed the driver first before you install the card (please refer to 2.2 Driver Installation) After the DLL driver installation is completed, you can now go on to install the PCI-1710/1710L/1710HG/1710HGL/1711/1711L/1716/ 1716L card in any PCI slot on your computer. But it is suggested that you should refer to the computer user manual or related documentations if you have any doubt.
Step 7: Connect appropriate accessories (68-pin cable, wiring terminals, etc. if necessary) to the PCI card. Step 8: Replace the cover of your computer chassis. Re-connect the cables you removed in step 2. Step 9: Plug in the power cord and turn on the computer . Note: . In case you installed the card without installing the DLL driver first, Windows 95/98 will recognize your card as an “unknown device” after rebooting, and will prompt you to provide the necessary driver.
Fig.2-3 The device name listed on the Device Manager Note: If your card is properly installed, you should see the device name of your card listed on the Device Manager tab. If you do see your device name listed on it but marked with an exclamation sign “!”, it means your card has not been correctly installed. In this case, remove the card device from the Device Manager by selecting its device name and press the Remove button. Then go through the driver installation process again.
2.4 Device Setup & Configuration The Device Manager program is a utility that allows you to set up, configure and test your device, and later stores your settings on the system registry. These settings will be used when you call the APIs of Advantech Device Drivers. Setting Up the Device Step 1: To install the I/O device for your card, you must first run the Device Installation program by accessing: Start/ Programs/ Advantech Automation/ Device Manager/ Advantech Device Manager.
Fig. 2-4 The Device Manager dialog box Fig.
Configuring the Device Step 4: On the Device Setting dialog box (Fig. 2-6), you can configure the voltage source either as External or Internal, and specify the voltage output range for the two D/A channels. Fig. 2-6 The Device Setting dialog box Note: ? .Users can configure the source of D/A reference voltage either as Internal or External, and select the output voltage range. When selecting voltage source as Internal, users have two options for the output voltage range : 0 ~ 5 V and 0 ~ 10 V.
Fig. 2-7. Fig. 2-7 The Device Name appearing on the list of devices box Note: As we have noted, the device name “000: ” begins with a device number “000”, which is specifically assigned to each card. The device number is passed to the driver to specify which device you wish to control. If you want to test the card device further, go right to the next section on the Device Testing.
2.5 Device Testing Following through the Setup and Configuration procedures to the last step described in the previous section, you can now proceed to test the device by clicking the Test Button on the Device Manager dialog box (Fig. 2-8). A Device Test dialog box will appear accordingly: Fig.
Note: n You can access the Device Test dialog box either by the previous procedure for the Device Installation Program or simply by accessing Start/Programs/ Advantech Automation/ Device Manager/ Advantech Device Manager. n All the functions are performed by software polling method. For high speed data acquirement or output, they have to use corresponding VC example like ADINT or ADDMA or ADBMDMA. Testing Analog Input Function Click the Analog Input tab to bring it up to the front of the screen.
Testing Analog Output Function (only for PCI-1710/ 1710HG/1711/1716) Click the Analog Output tab to bring it up to the foreground. The Analog Output tab allows you to output quasi-sine, triangle, or square waveforms generated by the software automatically, or output single values manually. You can also configure the waveform frequency and output voltage range. Fig.
Testing Digital Input Function Click the Digital Input tab to show forth the Digital Input test panel as seen below. Through the color of the lamps, users can easily discern whether the status of each digital input channel is either high or low. Fig.
Testing Digital Output Function Click the Digital Output tab to bring up the Digital Output test panel such as the one seen on the next page. By pressing the buttons on each tab, users can easily set each digital output channel as high or low for the corresponding port. Fig.
Testing Counter Function Click the Counter Tab to bring its test panel forth. The counter channel (Channel 0) offers the users two options: Event counting and Pulse out. If you select Event counting, you need first to connect your clock source to pin CNT0_CLK, and the counter will start counting after the pin CNT0_GATE is triggered. If you select Pulse Out, the clock source will be output to pin CNT0_OUT. You can configure the Pulse Frequency by the scroll bar right below it. Fig.
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CHAPTER 3 Signal Connections 35
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3. Signal Connections 3.1 Overview Maintaining signal connections is one of the most important factors in ensuring that your application system is sending and receiving data correctly. A good signal connection can avoid unnecessary and costly damage to your PC and other hardware devices. This chapter provides useful information about how to connect input and output signals to the PCI-1710/1710L/1710HG/1710HGL/1711/1711L/ 1716/1716L via the I/O connector. 3.
Note: The three ground references AIGND, AOGND, and DGND should be used discreetly each according to its designated purpose. Actually, we offer the individual GND pin for AI, AO and DIO to provide best signal quality. However, all the signals on the DA&C card need to refer to the same GND finally. So we test and choice a best point to connect AIGND, AOGND and DGND together. In short, this is base on the "single-point" ground principle.
Fig.
I/O Connector Signal Description Table 3-1 I/O Connector Signal Description Signal Name Reference Direction AI<0…15> AIGND Input AIGND - - AOGND Input AOGND Output AOGND - - DI<0..15> DO<0..15> DGND DGND Input Output DGND - - CNT0_CLK DGND Input CNT0_OUT CNT0_GATE DGND DGND Output Input PACER_OUT DGND Output TRG_GATE DGND Input EXT_TRG DGND Input +12V +5V DGND DGND Output Output AO0_REF AO1_REF AO0_OUT AO1_OUT 40 Description Analog Input Channels 0 through 15.
3.3 Analog Input Connections The PCI-1710/1710L/1710HG/1710HGL/1716/1716L supports both 16-channel Single-Ended or 8 differential A/D Input, however the PCI-1711/1711L only supports 16 single-ended analog inputs. Each individual input channel is software-selected. Single-ended Channel Connections The single-ended input configuration has only one signal wire for each channel, and the measured voltage (Vm) is the voltage of the wire as referenced against the common ground.
Fig. 3-2 Single-ended input channel connection Differential Channel Connections The differential input channels operate with two signal wires for each channel, and the voltage difference between both signal wires is measured. On the PCI-1710/1710L/1710HG/1710HGL/1716/1716L, when all channels are configured to differential input, up to 8 analog channels are available. If one side of the signal source is connected to a local ground, the signal source is ground-referenced.
To avoid the ground loop noise effect caused by common-mode voltages, you can connect the signal ground to the Low input. Fig. 3-3 shows a differential channel connection between a ground-reference signal source and an input channel on the PCI-1710/1710L/1710HG/1710HGL/1716/1716L. With this connection, the PGIA rejects a common-mode voltage V cm between the signal source and the PCI-1710/1710L/1710HG/1710HGL/1716/ 1716L ground, shown as V cm in Fig. 3-3. Fig.
against the AIGND. Fig. 3-4 shows a differential channel connection between a floating signal source and an input channel on the PCI-1710/1710L/ 1710HG/1710HGL/1716/1716L. In this figure, each side of the floating signal source is connected through a resistor to the AIGND. This connection can reject the common-mode voltage between the signal source and the PCI-1710/1710L/1710HG/1710HGL/1716/ 1716L ground. Fig.
and rb , for example, if the input impedance rs is 1 kW, and each of the two resistors is 100 kW, then the resistors load down the signal source with 200 kΩ (100 kΩ + 100 kW), resulting in a – 0.5% gain error. The following gives a simplified representation of the circuit and calculating process.
3.4 Analog Output Connections The PCI-1710/1710HG/1711/1716 provides two D/A output channels (PCI-1710L/1710HGL/1711L/1716L are not designed to have this function), AO0_OUT and AO1_OUT. Users may use the PCI-1710/1710HG/1711/1716 internally-provided precision -5V (-10V) reference to generate 0 to +5 V (+10 V) D/A output range. Users also may create D/A output range through external references, AO0_REF and AO1_REF. The external reference input range is +/-10 V.
3.5 Trigger Source Connections Internal Pacer Trigger Connection The PCI-1710/1710L/1710HG/1710HGL/1711/1711L/1716/1716L includes one 82C54 compatible programmable Timer/Counter chip which provides three 16-bit counters connected to a 10 MHz clock, each designated specifically as Counter 0, Counter 1 and Counter 2. Counter 0 is a counter which counts events from an input channel or outputing pulse. Counter 1 and Counter 2 are cascaded to create a 32-bit timer for pacer triggering.
3.6 Field Wiring Considerations When you use the PCI-1710/1710L/1710HG/1710HGL/1711/1711L/ 1716/1716L to acquire data from outside, noises in the environment might significantly affect the accuracy of your measurements if due cautions are not taken. The following measures will be helpful to reduce possible interference running signal wires between signal sources and the PCI-1710/1710L/1710HG/1710HGL/1711/1711L/ 1716/1716L.
signal cable at a right angle to the power line to minimize the undesirable effect. w The signals transmitted on the cable will be directly affected by the quality of the cable. In order to ensure better signal quality, we recommend that you use the PCL-10168 shielded cable.
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CHAPTER 4 Software Overview 51
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4. Software Overview This chapter gives you an overview of the software programming choices available and a quick reference to source codes examples that can help you be better oriented to programming. After following the instructions given in Chapter 2, it is hoped that you feel comfortable enough to proceed further. Programming choices for DAS cards: You may use Advantech application software such as Advantech DLL driver.
Register-level Programming Register-level programming is reserved for experienced programmers who find it necessary to write codes directly at the level of device registers. Since register-level programming requires much effort and time, we recommend that you use the Advantech DLL drivers instead. However, if register-level programming is indispensable, you should refer to the relevant information in Appendix C, Register Structure and Format, or to the example codes included on the companion CD-ROM. 4.
For instructions on how to begin programming works in each development tool, Advantech offers a Tutorial Chapter in the DLL Drivers Manual for your reference. Please refer to the corresponding sections in this chapter on the DLL Drivers Manual to begin your programming efforts. You can also take a look at the example source codes provided for each programming tool, since they can get you very well-oriented. The DLL Drivers Manual can be found on the companion CD-ROM.
Programming with DLL Driver Function Library Advantech DLL driver offers a rich function library to be utilized in various application programs. This function library consists of numerous APIs that support many development tools, such as Visual C++, Visual Basic, Delphi and C++ Builder.
error message. Or you can refer to the DLL Driver Error Codes Appendix in the DLL Drivers Manaul for a detailed listing of the Error Code, Error ID and the Error Message.
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CHAPTER Calibration 5 59
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5. Calibration This chapter provides brief information on PCI-1710/1710L/ 1710HG/1710HGL/1711/1711L/1716/1716L calibration. Regular calibration checks are important to maintain accuracy in data acquisition and control applications. We provide the calibration programs or utility on the companion CD-ROM to assist you in A/D and D/A calibration. Note: If you installed the program to another directory, you can find these programs in the corresponding subfolders in your destination directory.
voltage source. Note: Before you calibrate the A/D or D/A function, you must turn on the power at least 15 minutes to make sure the DAS card getting stable. 5.1 PCI-1710/1710L/1710HG/1710HGL Calibration Two calibration programs are included on the companion CD-ROM : ADCAL.EXE A/D calibration program DACAL.EXE D/A calibration program (only for PCI-1710/1710HG) These calibration programs are designed only for the DOS environment.
Fig.
A/D Calibration Regular and accurate calibration procedures ensure the maximum possible accuracy. The ADCAL.EXE calibration program leads you through the whole A/D offset and gain adjustment procedure. The basic steps are outlined below: 1. Set analog input channel AI0 as single-ended, bipolar, range ±5 V, and set AI1 as single-ended, unipolar, range 0 to 10 V. 2. Connect a DC voltage source with value equal to 0.5 LSB (-4.9959 V) to AI0. 3.
D/A Calibration (for PCI-1710/1710HG only) In a way similar to the ADCAL.EXE program, the DACAL.EXE program leads you through the whole D/A calibration procedure. You can either use the on-board -5 V (-10 V) internal reference voltage or use an external reference. If you use an external reference, connect a reference voltage within the range ±10 V to the reference input of the D/A output channel you want to calibrate. Adjust the full scale (gain) of D/A channel 0 and 1, with VR4 and VR5 respectively.
Then, run the ADCAL.EXE program to finish the self-A/D calibration procedure. 1. Set AI0 as differential, bipolar, range ±5 V and AI2 as differential, unipolar, range 0 to 10 V. 2. Connect DA0_OUT with codes equal to 4095 LSB (4.9959 V) to AI 0. Notice that the polarity of AI0 should be connected with reverse polarity (i.e. D/A + to A/D -, D/A - to A/D +). 3. Adjust VR2 until the output codes from the card's AI0 flicker between 0 and 1. 4. Connect DA0_OUT with codes equal to 4095 LSB (4.9959 V) to AI0. 5.
5.2 PCI-1711/1711L Calibration Three calibration programs are included on the companion CD-ROM : ADCAL.EXE A/D calibration program DACAL.EXE D/A calibration program (only for PCI-1711) SELFCAL.EXE D/A self-calibration program (only for PCI-1711) These calibration programs are designed only for the DOS environment.
VR Assignment There are four variable resistors (VRs) on the PCI-1711 card and two variable resistors (VRs) on the PCI-171L card. These variable resistors are to facilitate accurate adjustments for all A/D and D/A channels. Please refer to the following two figures for the VR positions. Fig.
A/D Calibration Regular and accurate calibration procedures ensure the maximum possible accuracy. The A/D calibration program ADCAL.EXE leads you through the whole A/D offset and gain adjustment procedure. The basic steps are outlined below: 1. Connect a DC voltage source of +9.995 V to AI0. 2. Connect AGND to AI1, AI2, AI3, AI4 and AI5. 3. Run the ADCAL.EXE program. 4.
You can adjust VR3 and VR4 until the D/A channel 0 and 1 output voltages approach the reference voltage (at least 1LSB), but with the reverse sign. For example, if Vref is -5V, then Vout should be +5V. If Vref is -10V, Vout should be +10V. Self A/D Calibration We know, in most cases, it is difficult to find a good enough DC voltage source for A/D calibration. We provide a self-adjusted A/D calibration program “SELFCAL. EXE” to help solve this problem. The steps of self-calibration are outlined as below: 1.
5.3 PCI-1716/1716L Calibration A calibration utility, AutoCali, is included on the companion CD-ROM : AutoCali.EXE PCI-1716/1716L calibration utility This calibration utility is designed for the Microsoft©Windows™ environment. Access this program from the default location: \Program Files\ADVANTECH\ADSAPI\Utilities\PCI1716 VR Assignment There is one variable resistor (VR1) on the PCI-1716/1716L to adjust the accurate reference voltage on the PCI-1716/1716L.
Calibration Utility The calibration utility, AutoCali.EXE, provides four functions - auto A/D calibration, auto D/A calibration, manual A/D calibration and manual D/A calibration. The program helps the user to easily finish the calibration procedures automatically; however, the user can calibrate the PCI-1716/1716L manually. Appendix E illustrated the standard calibration procedures for your reference. If you want to calibrate the hardware in your own way, these two sections will guide you.
Step 2: Select PCI-1716/1716L in the ADSDAQ dialog box. Fig. 5-4 Selecting the device you want to calibrate Step 3: After you start to calibrate the PCI-1716/1716L, please don’t forget to adjust VR1. Fig.
A/D channel Auto-Calibration Step 4: Click the Auto A/D Calibration tab to show the A/D channel auto-calibration panel (Fig. 5-6). Press the start button to calibrate A/D channels automatically. Fig. 5-6 Auto A/D Calibration Dialog Box Step 5: The first A/D calibration procedure is enabled (Fig. 5-7). Fig.
Step 6: The second A/D calibration procedure is enabled (Fig. 5-8) Fig. 5-8 A/D Calibration Procedure 2 Step 7: The third A/D calibration procedure is enabled (Fig. 5-9) Fig.
Step 8: Auto-calibration is finished. (Fig. 5-10) Fig. 5-10 A/D Calibration is finished D/A channel Auto-Calibration Step 9: Click the Auto D/A Calibration tab to show the D/A channel auto calibration panel. Please finish the A/D calibration procedure first before you start the D/A calibration procedure. There are two D/A channels in PCI-1716; select the output range for each channel and then press the start button to calibrate D/A channels (Fig. 5-11).
Fig. 5-11 Range Selection in D/A Calibration Step 10: D/A channel 0 calibration is enabled (Fig. 5-12) Fig.
Step 11: D/A channel 1 calibration is enabled (Fig. 5-13) Fig. 5-13 Calibrating D/A Channel 1 Step 12: Auto-calibration is finished (Fig. 5-14) Fig.
A/D channel Manual-Calibration Step 1: Click the Manual A/D Calibration tab to show the A/D channel manual calibration panel. Before calibrating, acquire the reference voltage from a precision standard voltage reference. Go to the Range form, select a channel and the target voltage range according to the input voltage value from a precision standard voltage reference (Fig. 5-15).
Fig. 5-15 Selecting Input Rage in Manual A/D Calibration panel Step 2: According to the difference between reference voltage and receiving data in PCI-1716/1716L, adjust the gain, bipolar offset and unipolar offset registers (Fig. 5-16) Fig.
Step 3: Adjust the registers until they fall between the input voltage from the standard voltage reference and the receiving voltage reflected in the Manual A/D Calibration tab. D/A channel Manual-Calibration Step 1: Click the Manual D/A Calibration tab to show the D/A channel manual calibration panel. Two D/A channels are individually calibrated . Before calibrating, output desired voltage from the D/A channels and measure it through an external precision multi-meter.
Step 2: For example, choose channel 0; select the Range and select the wished output voltage code or value from the radio buttons (Fig. 5-17 and Fig. 5-18). Fig. 5-17 & Fig.
Step 3: According to the difference between the output voltage from D/A channel and the value in the multi-meter, adjust the gain, bipolar offset and unipolar offset registers (Fig. 5-19) Fig. 5-19 Adjusting registers Step 4: Adjust registers until they fall between the output voltage from the D/A channel and the value in the multi-meter.
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Appendixes 85
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Appendix A. Specifications A.1 PCI-1710/1710L/1710HG/1710HGL Analog Input Channels Resolution FIFO Size PCI-1710/1710L Max. Sampling Rate1 PCI-1710HG/1710HGL Max. Sampling Rate Conversion Time Input range and Gain List for PCI-1710 / 1710L 16 single -ended or 8 differential or combination 12-bit 4k samples 100 KS/s Gain Speed Gain 0.5 Unipolar N/A Bipolar ±10 Gain Input range and Gain List Unipolar for PCI-1710HG / 1710HGL Bipolar Drift Small Signal Bandwidth for PGA Common mode voltage Max.
Analog Output Channels Resolution Output Range (Internal & External Reference) Using Internal Reference Using External Reference Accuracy Relative Differential Non-linearity Gain Error Slew Rate Drift Driving Capability Max. Update Rate Output Impedance Digital Rate Settling Time 2 12-bit 0 ~ +5V, 0 ~ +10 V 0 ~ + x V @ + x V ( - 10 ≦ x ≦ 10 ) ±0.5 LSB ±0.5 LSB (monotonic) Adjustable to zero 10 V /µ s 40 ppm / °C 3 mA 100 K samples /s 0.
General I/O Connector Type Dimensions Power Consumption 68-pin SCSI-II female 175 mm x 100 mm ( 6.9” x 3.9” ) Typical + 5 V @ 850mA Max.
A.2 PCI-1711/1711L Specifications Analog Input Channels Resolution FIFO Size Max. Sampling Rate Conversion Time Input Range and Gain List Drift ( ppm / ℃ ) Small Signal Bandwidth for PGA Max. Input Overvoltage Input Protect Input Impedance Trigger Mode Accuracy 16 Single -Ended 12-bit 1K samples 100 KS/s max. 10µs Gain Input 1 ±10V 1 15 25 1 2 ±5V 2 15 25 2 4 ±2.5V 4 15 25 4 8 16 ±1.25V ±0.625V 8 16 Zero 15 15 Gain 30 40 8 16 0.65 M 0.35 M Bandwidth 4.0 M Hz 2.0 M Hz 1.
Digital Input/Output Input Channels Input Voltage Input Load Low High Low High Output Channels Output Voltage Low High 16 0.4 V max. 2.4V min. 0.4 V max. @ - 0.2mA 2.7V min. @ 20 µ A 16 0.4 V max. @ + 8.0 mA (sink) 2.4V min. @ - 0.
A.3 PCI-1716/1716L Specifications Analog Input Channels Resolution FIFO Size Max. Sampling Rate Conversion Time 16 Single -Ended or 8rdiggerential or combinatio n 16-bit 1K samples 250 KS/s max. 2.5 µs Gain 0.5 1 2 4 8 Input range and Unipolar N/A 0~10 0~5 0~2.5 0~1.2 Gain List Bipolar ±10V ±5V ±2.5V ±1.25V ±0.625V Small Signal Gain 0.5 1 2 4 8 Bandwidth for 0.65 M Bandwidth 4.0 M Hz 4.0 M Hz 2.0 M Hz 1.5 M Hz PGA Hz Common mode ± 11 V max. ( operational ) Voltage Max.
Analog Input ( Only for PCI-1716 ) Channels Resolution Operation mode Throughput * Output Range ( Internal & External Reference) Accuracy Dynamic Performance Drift Driving Capability Output Impedance 2 16-bit Single output 200 KS/s max.
General I/O Connector Type Dimensions 68-pin SCSI-II female 175 mm x 100 mm ( 6.9” x 3.9” ) + 5 V @ 850mA Typical Power + 12V @ 600mA Consumption +5V@1A Max.
Appendix B. Block Diagrams B.
B.
B.
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Appendix C. Register Structure and Format C.1 Overview The PCI-1710/1710L/1710HG/1710HGL/1711/1711L/1716/1716L is delivered with an easy-to-use 32-bit DLL driver for user programming under the Windows 95/98/NT/2000/XP operating system. We advise users to program the PCI-1710/1710L/1710HG/ 1710HGL/1711/1711L/1716/1716L using the 32-bit DLL driver provided by Advantech to avoid the complexity of low-level programming by register.
C.2 I/O Port Address Map The PCI-1710/1710L/1710HG/1710HGL/1711/1711L/1716/1716L requires 32 consecutive addresses in the PC's I/O space. The address of each register is specified as an offset from the card's base address. For example, BASE+0 is the card's base address and BASE+7 is the base address plus seven bytes. The Table C-1 shows the function of each register of the PCI-1710/ 1710L/1710HG/1710HGL/1711/1711L/1716/1716L or driver and its address relative to the card's base address.
Table C-1 PCI-1710/1710L/1710HG/1710HGL/1711/1711L register format (Part 1) Base Address +decimal Read 7 6 1 CH3 CH2 0 AD7 AD6 5 4 3 1 0 Channel Number and A/D Data CH1 CH0 AD11 AD10 AD9 AD8 AD5 AD1 AD0 AD4 AD3 2 AD2 N/A 3 2 N/A 5 4 7 6 CNT0 ONE/FH Status Register IRQ F/F F/H F/E IRQEN EXT PACER SW GAT E N/A 9 8 N/A 11 10 N/A 13 12 N/A 15 14 101
Table C-1 PCI-1716/1716L register format (Part 2) Base Address +decimal Read 7 6 5 4 3 2 1 0 A/D Data 1 AD15 AD14 AD13 AD12 AD11 AD10 AD9 AD8 0 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 IRQ F/F F/H F/E GATE EXT PACER SW N/A 3 2 N/A 5 4 A/D Status Register 7 CAL 6 AD16/12 CNT0 ONE/FH IRQEN N/A 9 8 D/A channel 0 data 11 10 D/A channel 1 data 13 12 N/A 15 14 102
Table C-1 PCI-1710/1710L/1710HG/1710HGL/1711/1711L/ 1716/1716L register format (Part 3) Base Address +decimal Read 7 6 5 4 3 2 1 0 Digital Input 17 DI15 DI14 DI13 DI12 DI11 DI10 DI9 DI8 16 DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0 BD2 BD1 BD0 D2 D1 D0 D2 D1 D0 D2 D1 D0 N/A 19 18 Board ID (only for PCI-1716/1716L) 21 20 BD3 N/A 23 22 Counter 0 25 24 D7 D6 D5 D4 D3 Counter 1 27 26 D7 D6 D5 D4 D3 Counter 2 29 28 D7 D6 D5 D4 D3 N/A 31 30 103
Table C-1 PCI-1710/1710L/1710HG/1710HGL/1711/1711L register format (Part 4) Base Address +decimal Write 7 6 5 4 3 2 1 0 G1 G0 Software A/D Trigger 1 0 A/D Channel Range Setting 3 2 *S/D *B/U G2 Multiplexer Control 5 Stop channel 4 Start channel A/D Control Register 7 6 CNT0 ONE/FH IRQEN GATE EXT0 PACER SW Clear Interrupt and FIFO 9 Clear FIFO 8 Clear interrupt D/A Output Channel 0 11 10 DA7 DA6 DA5 DA4 DA11 DA10 DA9 DA8 DA3 DA2 DA1 DA0 D/A Output Channel 1 13 12 DA
Table C-1 PCI-1716/1716L register format (Part 5) Base Address +decimal Write 7 6 5 4 3 2 1 0 G1 G0 Software A/D Trigger 1 0 A/D Channel Range Setting 3 2 S/D B/U G2 Multiplexer Control 5 Stop channel 4 Start channel A/D Control Register 7 CAL 6 AD16/12 CNT0 ONE/FH IRQEN GATE EXT0 PACER SW Clear Interrupt and FIFO 9 Clear FIFO 8 Clear interrupt D/A Ou tput Channel 0 11 DA15 DA14 DA13 DA12 DA11 DA10 DA9 DA8 10 DA7 DA6 DA5 DA4 DA3 DA2 DA1 DA0 13 DA15 DA14
Table C-1 PCI-1710/1710L/1710HG/1710HGL/1711/1711L/ 1716/1716L register format (Part 6) Base Address +decimal Write 7 6 5 4 3 2 1 0 Digital Output 17 DO15 DO14 DO13 DO12 DO11 DO10 DOI9 DO8 16 DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0 Calibration Command and Data (only for PCI-1716/1716L) 19 18 D7 D6 D5 D4 CM3 CM2 CM1 CM0 D3 D2 D1 D0 D2 D1 D0 D2 D1 D0 D2 D1 D0 D2 D1 D0 N/A 21 20 N/A 23 22 Counter 0 25 24 D7 D6 D5 D4 D3 Counter 1 27 26 D7 D6 D5 D4 D3 Count
C.3 Channel Number and A/D Data — BASE+0 and BASE+1 BASE+0 and BASE+1 hold the result of A/D conversion data. For PCI-1710/1710L/1710HG/1710HGL/1711/1711L, the 12 bits of data from the A/D conversion are stored in BASE+1 bit 3 to bit 0 and BASE+0 bit 7 to bit 0.BASE+1 bit 7 to bit 4 hold the source A/D channel number.
For PCI-1716/1716L, the 16 bits of data from the A/D conversion are stored in BASE+1 bit 7 to bit 0 and BASE+0 bit 7 to bit 0.
C.4 Software A/D Trigger — BASE+0 You can trigger an A/D conversion by software, the card's on-board pacer or an external pulse. BASE+6, Bit 2 to bit 0, select the trigger source. (see Section C.7, Control Register -- BASE+6 ) If you select software triggering, a write to the register BASE+0 with any value will trigger an A/D conversion.
C.5 A/D Channel Range Setting — BASE+2 Each A/D channel has its own input range, controlled by a gain code stored in the on-board RAM. To change the range code for a channel: Write the same channel in BASE+4 (the start channel) and ? BASE+5 (the stop channel) (refer to Section C.6). Write the gain code to BASE+2 bit 0 to bit 2.
Table C-7 lists the gain codes for the PCI-1711/1711L. Table C-5 Gain codes for PCI-1710/1710L PCI-1710/1710L Gain Input Range(V) Gain Code B/U G2 G1 G0 1 -5 to +5 0 0 0 0 2 -2.5 to +2.5 0 0 0 1 4 -1.25 to +1.25 0 0 1 0 8 -0.625 to +0.625 0 0 1 1 0.5 -10 to +10 0 1 0 0 N/A 0 1 0 1 N/A 0 1 1 0 N/A 0 1 1 1 1 0 to 10 1 0 0 0 2 0 to 5 1 0 0 1 4 0 to 2.5 1 0 1 0 8 0 to 1.
Table C-6 Gain codes for PCI-1710HG/1710HGL PCI-1710HG/1710HGL Gain 112 Input Range(V) Gain Code B/U G2 G1 G0 1 -5 to +5 0 0 0 0 10 -0.5 to +0.5 0 0 0 1 100 -0.05 to +0.05 0 0 1 0 1000 -0.005 to +0.005 0 0 1 1 0.5 -10 to +10 0 1 0 0 5 -1 to +1 0 1 0 1 50 -0.1 to +0.1 0 1 1 0 500 -0.01 to +0.01 0 1 1 1 1 0 to 10 1 0 0 0 10 0 to 1 1 0 0 1 100 0 to 0.1 1 0 1 0 1000 0 to 0.
Table C-7 Gain codes for PCI-1711/1711L PCI-1711/1711L Gain Gain Code Input Range(V) G2 G1 G0 1 -10 to +10 0 0 0 2 -5 to +5 0 0 1 4 -2.5 to +2.5 0 1 0 8 -1.25 to +1.25 0 1 1 16 -0.625 to +0.625 1 0 0 Example: To set channel 3 as gain=1 1. Write channel 3 to BASE+4 as 00000011. 2. Write channel 3 to BASE+5 as 00000011. 3. Refer to the gain code list, write gain=1 to BASE+2 as 00000000.
C.6 MUX Control — BASE+4 and BASE+5 Table C-8 Register for multiplexer control Write Bit # Multiplexer Control 7 6 5 4 3 2 1 0 BASE + 5 STO3 STO2 STO1 STO0 BASE + 4 STA3 STA2 STA1 STA0 STA3 ~ STA0 Start Scan Channel Number STO3 ~ STO0 Stop Scan Channel Number n When you set the gain code of analog input channel n, you should set the Multiplexer start & stop channel number to channel n to prevent any unexpected errors.
? BASE+4 bit 3 to bit 0, STA3 ~ STA0, hold the start scan channel number. ? BASE+5 bit 3 to bit 0, STO3 ~ STO0, hold the stop scan channel number. Writing to these two registers automatically initializes the scan range of the Multiplexer. Each A/D conversion trigger also sets the Multiplexer to the next channel. With continuous triggering, the Multiplexer will scan from the start channel to the stop channel and then repeat. The following examples show the scan sequences of the Multiplexer.
For example, the AI0 and AI1 is a pair. When in single-ended mode, we can get data from AI0 and AI1 separately. But if we set them as differential mode, the results polling AI0 and AI1 will be the same. That is if we set the AI0 and AI1 as a differential input channel, we can get the correct result no matter we polling channel 0 or channel 1. But if we want to use the multiple channels input function, the things will be a little bit different.
Warning! Only even channels can be set as differential. An odd channel will become unavailable if its preceding channel is set as differential.
C.7 Control Register — BASE+6 The write-only register BASE+6 and BASE+7 allows users to set an A/D trigger source and an interrupt source. Table C-9 Control Register Write A/D Status Register Bit # 7 BASE + 7 * CAL BASE + 6 *AD16/12 6 5 4 3 2 1 0 CNT0 ONE/FH IRQEN GATE EXT PACER SW *: AD16/12 and CAL are only supported for PCI-1716/1716L SW PACER EXT Software trigger enable bit 1 enable 0 disable. Pacer trigger enable bit 1 enable 0 disable.
IRQEN ONE/FH CNT0 Interrupt enable bit. 0 Disable 1 Enable Interrupt source bit 0 Interrupt when an A/D conversion occurs 1 Interrupt when the FIFO is half full.
connected to 68 pin SCSI-II connector respectively. 1 A/D and D/A calibration mode The wiring becomes that AI0 is connected to 0 V (AGND), AI2 is connected to +5 V, AI4 is connected to AO0, and AI6 is connected to AO1 automatically.
C.8 Status Register — BASE+6 and BASE+7 The registers of BASE+6 and BASE+7 provide information for A/D configuration and operation. Table C-10 Status Register Write A/D Control Register Bit # 7 BASE + 7 * CAL BASE + 6 *AD16/12 6 CNT0 5 ONE/FH 4 IRQEN 3 2 1 0 IRQ F/F F/H F/E GATE EXT PACER SW *: CAL is only supported for PCI-1716/1716L The content of the status register of BASE+6 is the same as that of the control register.
C.9 Clear Interrupt and FIFO — BASE+8 and BASE+9 Writing data to either of these two bytes clears the interrupt or the FIFO. Table C-11 Register to clear interrupt and FIFO Write Bit # Clear Interrupt and FIFO 7 6 5 4 3 BASE + 9 Clear FIFO BASE + 8 Clear Interrupt C.10 D/A Output Channel 0 — BASE+11 2 1 0 BASE+10 and The PCI-1716 provides the innovative design as gate control for Analog Output function.
C.11 D/A Output Channel 0 — BASE+11 BASE+10 and The write-only registers of BASE+10 and BASE+11 accept data for D/A Channel 0 output. PCI-1710L/1710HGL/1711L/1716L The PCI-1710L/1710HGL/1711L/1716L is not equipped with the D/A functions.
C.12 D/A Output Channel 1 — BASE+13 BASE+12 and The PCI-1716 provides the innovative design as gate control for Analog Output function. It works as general Analog Output function when you disable the flag (bit 11 (DA1_LDEN) of BASE+14). That means the data will be output immediately. However, when you enable the flag, you need to read these two registers BASE+12 and BASE+13 to output the data to the Analog Output channel.
C.13 D/A Output Channel 1 — BASE+13 BASE+12 and The write-only registers of BASE+12 and BASE+13 accept data for D/A channel 1 output. PCI-1710L/1710HGL/1711L/1716L The PCI-1710L/1710HGL/1711L/1716L is not equipped with the D/A functions.
C.14 D/A Reference Control — BASE+14 The write-only register of BASE+14 allows users to set the D/A reference source. PCI-1710L/1710HGL/1711L/1716L The PCI-1710L/1710HGL/1711L/1716L is not equipped with the D/A functions.
DAn_B/U DAn_I/E for D/A output channel n 0 Bipolar 1 Unipolar Internal or external reference voltage for D/A output channel n 0 Internal source 1 External source DAn_LDEN for Gate Control of D/A output channel n (Please refer to C.10 and C.
C.15 Digital I/O Registers — BASE+16 and BASE+17 The PCI-1710/1710L/ 1710HG/1710HG/1711/1711L/1716/1716L offers 16 digital input channels and 16 digital output channels. These I/O channels use the input and output ports at addresses BASE+16 and BASE+17.
C.16 Calibration Registers — BASE+18 and BASE+19 The PCI-1716/1716L offers Calibration registers BASE+16 and BASE+17 for user to calibrate the A/D and D/A.
Table C-21 Calibration Command and Data Register PCI-1716/1716L Command Code Meaning 130 CM3 CM2 CM1 CM0 A/D bipolar offset adjust 0 0 0 0 A/D unipolar offset adjust 0 0 0 1 PGA offset adjust 0 0 1 0 A/D gain adjust 0 0 1 1 D/A 0 gain 1 adjust (10 V) 0 1 0 0 D/A 0 gain 2 adjust (5 V) 0 1 0 1 D/A 0 bipolar offset adjust 0 1 1 0 D/A 0 unipolar offset adjust 0 1 1 1 D/A 1 gain 1 adjust (10 V) 1 0 0 0 D/A 1 gain 2 adjust (5 V) 1 0 0 1 D/A 1 bipolar offset
C.17 Board ID Registers — BASE+20 The PCI-1710/1710L/1710HG/1710HGL/1716/1716L offers Board ID register BASE+20. With correct Board ID settings, user can easily identify and access each card during hardware configuration and software programming. Table C-22 Register for Board ID Read Bit # Board ID 7 6 5 BASE + 20 4 3 2 1 0 BD3 BD2 BD1 BD0 C.
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Appendix D. 82C54 Counter Chip Function D.1 The Intel 82C54 The PCI-1710/1710L/1710HG/1710HGL/1711/1711L/1716/1716L uses one Intel 82C54 compatible programmable interval timer/counter chip. The popular 82C54 offers three independent 16-bit counters, counter 0, counter 1 and counter 2. Each counter has a clock input, control gate and an output. You can program each counter for maximum count values from 2 to 65535. The 82C54 has a maximum input clock frequency of 10 MHz.
Counter 1 & 2 Counter 1 and counter 2 of the counter chip are cascaded to create a 32-bit timer for the pacer trigger. A low-to-high edge of counter 2 output (PACER_OUT) will trigger an A/D conversion. At the same time, you can use this signal as a synchronous signal for other applications.
D.2 Counter Read/Write and Control Registers The 82C54 programmable interval timer uses four registers at addresses BASE + 24(Dec), BASE + 26(Dec), BASE + 28(Dec) and BASE + 30(Dec) for read, write and control of counter functions.
Description: SC1 & SC0 Select counter Counter SC1 SC0 0 0 0 1 0 1 2 1 0 Read-back command 1 1 RW1 & RW0 Select read / write operation Operation RW1 RW0 Counter latch 0 0 Read/write LSB 0 1 Read/write MSB 1 0 Read/write LSB first, 1 1 then MSB M2, M1 & M0 Select operating mode 136 M2 M1 M0 Mode Description 0 0 0 0 Stop on terminal count 0 0 1 1 Programmable one shot X 1 0 2 Rate generator X 1 1 3 Square wave rate generator 1 0 0 4 Software triggered
BCD Select binary or BCD counting BCD Type 0 Binary counting 16-bits 1 Binary coded decimal (BCD) counting If you set the module for binary counting, the count can be any number from 0 up to 65535. If you set it for BCD (Binary Coded Decimal) counting, the count can be any number from 0 to 9999. If you set both SC1 and SC0 bits to 1, the counter control register is in read-back command mode.
by C2 to C0 contains a byte which shows the status of the counter.
D.3 Counter Operating Modes MODE 0 – Stop on Terminal Count The output will initially be low after you set this mode of operation. After you load the count into the selected count register, the output will remain low and the counter will count. When the counter reaches the terminal count, its output will go high and remain high until you reload it with the mode or a new count value. The counter continues to decrement after it reaches the terminal count.
pulses, the present period will not be affected, but the subsequent period will reflect the value. The gate input, when low, will force the output high. When the gate input goes high, the counter will start from the initial count. You can thus use the gate input to synchronize the counter. With this mode the output will remain high until you load the count register. You can also synchronize the output by software.
(N+1)/2 counts and low for (N-1)/2 counts. MODE 4 –Software-Triggered Strobe After the mo de is set, the output will be high. When the count is loaded, the counter will begin counting. On terminal count, the output will go low for one input clock period then go high again. If you reload the count register during counting, the new count will be loaded on the next CLK pulse. The count will be inhibited while the GATE input is low.
D.4 Counter Operations Read/Write Operation Before you write the initial count to each counter, you must first specify the read/write operation type, operating mode and counter type in the control byte and write the control byte to the control register [BASE + 30(Dec)]. Since the control byte register and all three counter read/write registers have separate addresses and each control byte specifies the counter it applies to (by SC1 and SC0), no instructions on the operating sequence are required.
latch commands, one for each counter latched. The read-back command can also latch status information for selected counter(s) by setting STA bit = 0. The status must be latched to be read; the status of a counter is accessed by a read from that counter. The counter status format appears at the beginning of the chapter. Counter Latch Operation Users often want to read the value of a counter without disturbing the count in progress.
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Appendix E. PCI-1716/1716L Calibration (Manually) E.1 A/D Calibration Regular and proper calibration procedures ensure the maximum possible accuracy. It is easy to complete the A/D calibration procedure automatically (i.e. through software calibration) by executing the A/D calibration program AutoCali.EXE. Therefore, it is not necessary to adjust the hardware settings of the PCI-1716/1716L. However, the following calibration steps are also provided for your reference in case manual calibration is needed: 1.
discrepancy is less then 2 LSB. If so, to go to next step. Otherwise, you must change the value and repeat all the procedure in this step again until the discrepancy is less then 2 LSB. 4. Adjust the BIPOLAR offset voltage. First, writing any value to BASE+9 to clear FIFO. Then to set A/D channel to channel 0, and to set the range as –5 V to +5 V. 5.
to clear FIFO. Then to set A/D channel to channel 2, and to set the range as -5 V to +5 V. 9. Writing the value from 0x0300 to 0x03FF sequentially to Calibration Command and Data register (BASE+18), and get each bipolar range’s data by software trigger A/D method. Be noted that to repeat this procedure 1000 times then to average those data for each value. After that, to see whether the average data is close to 65534.6. If so, to go to next step.
E.2 D/A Calibration (for PCI-1716 only) You can select an on-board +5V or +10V internal reference voltage or an external voltage as your analog output reference voltage. If you use an external reference, connect the reference voltage within the ±10V range to the reference input of the D/A output channel you want to calibrate. Then adjust the gain value, unipolar offset voltage, bipolar offset voltage, respectively, of D/A channels 0 and 1 with the Calibration Command and Data register (BASE+18).
BASE+9 to clear FIFO. Then to set the A/D range as 0 V to 10 V, and to set the D/A range as 0 V to 10 V. Next, writing 0xFFFF to corresponding D/A registers (BASE+10 and BASE+12). 3. Writing the value from 0x0400 to 0x04FF sequentially to Calibration Command and Data register (BASE+18), and get each bipolar range’s data by software trigger A/D method. Be noted that to repeat this procedure 1000 times then to average those data for each value. After that, to see whether the average data is close to 65534.6.
corresponding D/A registers (BASE+10 and BASE+12). 7. Writing the value from 0x0600 to 0x06FF sequentially to Calibration Command and Data register (BASE+18), and get each bipolar range’s data by software trigger A/D method. Be noted that to repeat this procedure 1000 times then to average those data for each value. After that, to see whether the discrepancy is less then 0.4 LSB. If so, to go to next step.
Table E-2 D/A binary code table A/D code Mapping Voltage Hex. Dec. Bipolar Unipolar 0000h 0 -FS 0 7FFFh 32767 -1 LSB 0.5 FS – 1 LSB 8000h 32768 0 0.
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Appendix F. Screw-terminal Board F.1 Introduction The PCLD-8710 Screw-terminal Board provides convenient and reliable signal wiring for the PCI-1710/1710L/1710HG/1710HGL/ 1711/1711L/1716/1716L, both of which have a 68-pin SCSI-II connector. This screw terminal board also includes cold junction sensing circuitry that allows direct measurement of thermocouples transducers. Together with software compensation and linearization, every thermocouple type can be accommodated.
F.2 Features w Low-cost screw-terminal board for the PCI-1710/1710L/1710HG/ 1710HGL/1711/1711L/1716/1716L with 68-pin SCSI-II connector. w On-board CJC (Cold Junction Compensation) circuits for direct thermocouple measurement. w Reserved space for signal-conditioning circuits such as low-pass filter, voltage attenuator and current shunt. w Industrial-grade screw-clamp terminal blocks for heavy-duty and reliable connections. w DIN-rail mounting case for easy mounting.
