User manual

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Chapter 3 Award BIOS Setup.........................................36
3.1 Introduction ..................................................................... 36
3.1.1 CMOS RAM Auto-backup and Restore ....................... 36
3.2 Entering Setup................................................................. 37
Figure 3.1:Award BIOS Setup initial screen ................ 37
3.3 Standard CMOS Setup .................................................... 37
Figure 3.2:Standard CMOS features screen ................. 37
Figure 3.3: Standard CMOS features IDE Channel screen ... 38
3.4 Advanced BIOS Features................................................ 39
Figure 3.4:Advanced BIOS features screen - 1 ............ 39
Figure 3.5:Advanced BIOS features screen - 2 ............ 39
3.4.1 Hard Disk Boot Priority................................................ 40
3.4.2 Virus Warning............................................................... 40
3.4.3 CPU L1 & L2, L3 Cache .............................................. 40
3.4.4 Hyper-Threading Technology....................................... 40
3.4.5 Quick Power On Self Test ............................................ 40
3.4.6 First/Second/Third Boot Device ................................... 40
3.4.7 Boot Other Device ........................................................ 40
3.4.8 Swap Floppy Drive ....................................................... 40
3.4.9 Boot Up Floppy Seek.................................................... 40
3.4.10 Boot Up NumLock Status............................................. 41
3.4.11 Gate A20 Option ........................................................... 41
3.4.12 Typematic Rate Setting................................................. 41
3.4.13 Typematic Rate (Chars/Sec) ......................................... 41
3.4.14 Typematic Delay (msec)............................................... 41
3.4.15 Security Option ............................................................. 41
3.4.16
APIC Mode (Advanced Programmable Interrupt Controller) 41
3.4.17 MPS Version Control For OS....................................... 42
3.4.18 Console Redirection...................................................... 42
3.4.19 Baud Rate...................................................................... 42
3.4.20 Agent Connect via ........................................................ 42
3.4.21 Agent wait time (sec).................................................... 42
3.4.22 Agent after boot ............................................................ 42
3.5 Advanced Chipset Features............................................. 43
Figure 3.6: Advanced Chipset features screen.............. 43
3.5.1 System BIOS Cacheable............................................... 43
3.5.2 Video Bios Cacheable................................................... 43
3.5.3 Memory Hole At 15M-16M ......................................... 44
3.5.4 Delay Prior to Thermal ................................................. 44
3.5.5 MCH Compliance Mode............................................... 44
3.5.6 Memory RAS Feature................................................... 44
3.5.7 Init Display first ............................................................ 44
3.6 Integrated Peripherals...................................................... 45
Figure 3.7:Integrated peripherals.................................. 45
Figure 3.8:On-Chip IDE Device................................... 45