User manual

As is fully explained in the TC section of the document, for these modes
the counter is actually stopped or disarmed following the active-going
source edge which drives the counter out of TC. In other words, since a
counter in the TC state always counts, irrespective of it's gating of
arming status, the stopping or disarming of the count sequence is
delayed until TC is terminated.
Counter mode table:
(N: No gate control, L: Level gate control, E: Edge gate
control)
Table D-1 PCI-1780 counter mode
Counter Mode
A B C D E F G H I J K L
Special Gate (CM6)
0 0 0 0 0 0 0 0 0 0 0 0
Reload Source (CM5)
0 0 0 0 0 0 1 1 1 1 1 1
Repetition (CM4)
0 0 0 1 1 1 0 0 0 1 1 1
Gate Control (CM15~CM12)
N L E N L E N L E N L E
Count to TC once, then disarm
Count to TC twice, then disarm
Count to TC repeatedly without disarming
Gate input dose not gate counter input
Count only during active gate level
Start count on active gate edge and stop count on next TC
Start count on active gate edge and stop count on second TC
Start count on active gate edge and stop count on inactive gate edge
Reload counter from Load Register on TC
Reload counter on each TC, alternating reload source between Load
and Hold Registers
Counter Mode
M N O P Q R S T U V W X
Special Gate (CM6)
1 1 1 1 1 1 1 1 1 1 1 1
Reload Source (CM5)
0 0 0 0 0 0 1 1 1 1 1 1
Repetition (CM4)
0 0 0 1 1 1 0 0 0 1 1 1
Gate Control (CM15~CM12)
N L E N L E N L E N L E
Count to TC once, then disarm
Count to TC twice, then disarm
Count to TC repeatedly without disarming
Gate input dose not gate counter input
Count only during active gate level
Start count on active gate edge and stop count on next TC
Start count on active gate edge and stop count on second TC
Start count on active gate edge and stop count on inactive gate edge
Reload counter from Load Register on TC
Reload counter on each TC, alternating reload source between Load
and Hold Registers
Note: Counter modes M, N, P, Q, S, T, V, W are identical to A, B, D, E, G, H, J, K.
50