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C.8 Interrupt control — BASE+42H
Table C-7 PCI-1780 Register for interrupt control
Base Addr.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Interrupt control
42H W
DI0 C7 C6 C5 C4 C3 C2 C1 C0
Cn Counter interrupt enable bit (n: 0 ~ 7)
0 Disable interrupt for this counter
1 Enable interrupt for this counter
DI0 Interrupt enable bit
0 Disable interrupt for DI0
1 Enable interrupt for DI0
C.9 Interrupt status — BASE+42H
Table C-8 PCI-1780 Register for interrupt status
Base Addr.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Interrupt control
42H R
DI0 C7 C6 C5 C4 C3 C2 C1 C0
Cn Counter interrupt status bit (n: 0 ~ 7)
0 No interrupt occurred
1 Interrupt occurred
DI0 Interrupt status bit
0 No interrupt occurred form DI0
1 Interrupt occurred form DI0
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