User manual
Table Of Contents
- UTCA-5503
- Contents
- 1 Board Specification
- 2 Applications and Overview
- 3 Mezzanine Module Options
- 4 Operations
- 5 Firmware Upgrades
- 6 Overview of Supported Features and Known Limitations
- A MCH Pin List, Connector 1
- B IPMI/PICMG Command Subset Supported by the MCMC
- C IPMI/PICMG Command Subset Supported by the Carrier Manager
- D IPMI/PICMG Command Subset Supported by the uShM
3 UTCA-5503 User Manual
Chapter 1 Board Specification
1.2 Advantech UTCA-5503 Features
1.2.1 MCMC
The MCMC on UTCA-5503 is built based on Pigeon Point Systems’ (PPS) hardware/
software reference design kit for MCMC.
1.2.1.1 H8S Microprocessor
Renesas Technology’s HD64F2166 (referenced hereafter as the H8S) is used as the
microcontroller for the MCMC implementation on Advantech’s MCH (aMCH). This
microcontroller contains a Renesas’ H8S/2000 CPU as its core architecture, in addi-
tion to peripheral functions. The H8S is a highly integrated microcontroller that has
on-chip Flash and SRAM memories. The peripheral functions of the H8S used in the
aMCH MCMC design include the I2C controllers, free-running timer, watchdog timer
(WDT), Serial Communication Interface (SCI), Low Pin Count (LPC) interface, Ana-
log-to-Digital Converter (ADC), and GPIO. The LPC interface is optional for the
implementation of the to-be-developed PCB Level 3 or PCB3 for short.
1.2.1.2 IPMB and I2C Implementations
The MCMC has six hardware I2C controllers, which are used as listed below.
Safety and others UL94V0, RoHS
EMC
· FCC class B
· >3dB margin targeted for single board within system
Standards compliance
PICMG MicroTCA.0 rev1.0, PICMG AMC.0 rev2.0, PICMG AMC.3
rev1.0, IPMI v1.5 rev1.1, IPMB communication protocol rev1.1
Table 1.1: Advantech UTCA-5503 MCH Technical Data
Table 1.2: H8S I2C Bus Assignment
MCMC I2C Used for
0 Carrier FRU I2C
1 reserved
2 IPMB0-A
3 IPMB0-B
4 MCMC private I2C
5 Radial IPMB / MCH Crossover IPMB