User manual

MIC-3392MIL User Manual 44
3.2.2 Extended Pre-heat Mode
The extended preheat mode will have the same implementation as the standard pre-
heat mode but will add one extra feature:
! During the warm up phase, the BMC will repeatedly de-assert the system reset
for PREHEAT_TON and then assert it for PREHEAT_TOFF to cause extra
power dissipation by CPU and chipset.
3.2.3 BMC Communication Interface to the x86 System
The BMC will provide a LPC based communication interface to the x86 system, pro-
viding access to internal registers. Some of the register settings will be user config-
urable defaults which will be stored in the SEEPROM.
The LPC interface will be interrupt based, and the read/write accesses to the internal
registers will be carried out within the interrupt handler. If a write access has taken
place and the SEEPROM will have to be updated, the interrupt handler will set a glo-
bal flag to indicate to the application main loop that updated settings will need to be
written to the SEEPROM.
The LPC based register interface will consist of an index and data register. The fol-
lowing table shows the internal register map pertaining to the pre-heat function.
Note! PREHEAT_TON = Time duration [second] of system reset de-assertion
in extended pre-heat mode.
PREHEAT_TOFF = Time duration [second] of system reset assertion in
extended pre-heat mode.