Service manual

1
ORTEC MODEL 584
CONSTANT-FRACTION DISCRIMINATOR
1. DESCRIPTION
1.1. PURPOSE
The ORTEC 584 allows excellent time resolution
from all commonly used detectors such as high-
purity germanium (HPGe), surface barrier, fast
plastic, Nal(TI), and photomultiplier tubes. This unit
accepts input pulses in the range of 0 to -5 V and
generates NIM fast negative outputs and a slow
positive output that are based on the constant- In the constant-fraction technique, an input signal to
fraction time derivation technique. The 584 the constant-fraction circuitry is delayed, and a
operates as an integral discriminator and provides fraction of the undelayed pulse is subtracted from it.
excellent timing characteristics for a wide dynamic A bipolar signal is generated, and its zero crossing
range of input signal amplitudes. Three timing is detected and used to produce an output logic
modes are provided in the 584: constant fraction pulse.
(CF), constant fraction with slow rise time reject
(SRT), and leading edge (LE). Also, the 584 can be
gated by the Bin Gate, a slow positive NIM signal,
or a fast negative NIM signal.
The input impedance of the 584 is 50 , and the
NIM fast logic output signals are designed for
termination in 50 . A NIM slow positive SCA
output is also furnished with an output impedance
<10 .
1.2. DISCRIMINATION CHARACTERISTICS
The 584 operates as an integral discriminator. Each
input pulse that exceeds the lower-level threshold
(adjustable on the front panel) can cause a set of
timing output signals to be generated. This set of
signals includes two independent fast negative NIM
signals, nominally 5 ns in width and a slow positive
NIM signal adjustable in width from
0.5 µs to 2.5
µs.
The 584 includes a slow rise time reject function,
selectable by the operator, and a variable width
blocking one-shot. The slow rise time reject circuit
can be used to inhibit the discriminator response to
input signals that would cause leading edge timing.
A blocking one-shot pulse is initiated
simultaneously with the timing output signals. The
blocking one-shot prohibits further timing output
signals from being produced during the adjusted
blocking period. A negative NIM blocking output
pulse is provided through a front panel connector.
The width of the blocking output is determined by
the width set for the blocking one-shot.
1.3. CONSTANT-FRACTION PRINCIPLE
The constant-fraction shaping delay is controlled by
the length of cable that is connected externally
between the two Delay connectors on the front
panel. The shaping delay should be optimized for
each specific application. This optimization requires
prior knowledge of the rise time and nominal width
of the input signals to the 584.
1.4. INPUT/OUTPUT CHARACTERISTICS
The 584 accepts negative input signals to -5 V
without saturation. If an input signal satisfies the
logic conditions established with the 584, four
output pulses are initiated simultaneously. Two
timing output signals are provided through front
panel connectors; these are independent negative
NIM fast logic pulses nominally 5 ns in width. A
positive NIM output is provided through a front
panel BNC. The blocking output is a negative
current pulse that is a NIM fast logic pulse; its width
is determined by the front panel Width control
setting. The blocking output is furnished through a
front panel connector. The width of the blocking
output is set by the period of the internal blocking
one-shot, which is variable in the range of 10 ns to
1000 ns. The purpose of the blocking one-shot is
to prohibit further timing output signals from being
generated during the blocking period.