Service manual

7
pulse. This clipped pulse is furnished through as in the CF mode. However, if t occurs prior to a
current drivers CD1 and CD2 to the timing outputs, signal at the output of G3, the Q output, FF2, will
and to an inverting ECL-to-TTL converter to not change state when clocked by the output of G1.
produce the positive output. The width of the Thus all output signals will be blocked at G6.
positive output is adjustable from 0.5 µs to 2.5 µs
by a printed-wiring board mounted potentiometer. Four separate gating modes are available. A rear
Additional output signals are blocked by the panel locking toggle switch selects either Gated or
blocking one-shot composed of FF3, A4, C2, and Ungated operation. When set in the Ungated
the Blocking Width control. The blocking period is position, a high state is connected to the D inputs of
determined by the adjustable delay time to reset FF3 and FF4, which enables output signals to be
FF3. The blocking period is variable from 10 ns to generated. When set in the Gated position, a
1000 ns and can be monitored at the front panel printed wiring-board jumper must be set to select
connector. the Bin Gate (pin 36 of the NIM power connector
block), a slow positive NIM input via a rear panel
When operated in the Leading Edge timing mode
(LE), the timing mode switch disables G1 and G3
while enabling G2. The circuit operation is similar to
the CF mode except that the LE discriminator
output, through G2, clocks FF1 and FF2 to produce
all the output signals. The timing output signals are
no longer related in time to the zero crossing time
of the constant-fraction signal. Rather, all output
signals are related to the time the leading edge of
the input signal crosses the LE threshold level.
When operated in the Slow Rise Time Reject mode
(SRT), the timing mode switch disables G2 and
enables G1 and G3. Operation differs from the CF
only by the function of FF2. The inverted output of
the LE discriminator gates G3 causing its output to
switch to a low state on a time constant set by C1.
If the output of G3 decays below the threshold
level of FF2 prior to t , the unit functions the same
cf
cf
connector, or a fast negative NIM signal via the
same rear panel connector. The slow positive NIM
signal and the Bin Gate are converted to ECL signal
levels by a NIM-to-ECL converter. The fast
negative NIM signal is converted to ECL signal
levels by a fast NIM-to-ECL converter and A3. All
gating options are wired at G7.
The input power requirements are +12 V, -12 V,
-6 V, and -24 V. A rear panel switch allows use of
the -12 V supply instead of the -6 V supply to
provide the ECL logic current. These levels are all
obtained from the bin power supply. Additional
voltage levels of +5 V and -5.2 V are also required.
These voltages are obtained from regulators on the
printed wiring board.