Service manual

6
Fig. 5.1. Simplified Block Diagram of the ORTEC 584
Constant Fraction Discriminator.
The CF signal crosses the logic threshold of G1 at The G1 output signal clocks the high state at D to
constant-fraction time, t . Constant-fraction time is the Q output of FF1. The Q output of FF1 is
cf
determined by the selection of the external delayed by DL1, inverted by A2, and applied to the
constant-fraction shaping delay, t , subject to the input of G6. The D input of FF2 is in the low state
d(Ext)
rise times and pulse shapes of the input signals. A since the timing mode switch in the CF position
fixed internal delay of about 0.8 ns must be added applies a high state to the input of G3.
to t to determine the total constant-fraction
d(Ext)
shaping delay, t . Note that the time of Note that a previous reset signal preset the Q
d(Tot)
occurrence of the output of G1 is directly related to output of FF2 to a high state. When the G1 output
t only if the arming signal from LE arrives at the signal clocks FF2, through G4, the D input low state
cf
input of G1 prior to the negative-going excursion of is clocked to the Q output which enables G6 to pass
the output of CFA. If the signal from LE arrives at the timing signal from A2. The output of A2 initiates
G1 later in time, the output signal from G1 will have reset for FF1 and FF2 through G5. The Q output of
time movement relative to the input signal. This FF2 is reset to a high state which produces a pulse
type of time movement is often referred to as <10 ns wide at the output of G6.
leading edge time walk.
Access to the inverted CF signal is provided by the output shaping circuitry. Assuming that the rear
front panel CF Mon connector. This signal is panel switch is in the Ungated position, a high state
buffered by R3 and has a typical amplitude of 40 is present on the D inputs of FF3 and FF4. The
mV peak-to-peak when viewed with a 50 ohm input output of G6 clocks FF3 causing the Q output to
impedance oscilloscope. The baseline of the CF change states which, in turn, clocks FF4, causing
Mon signal has a
-
60 mV dc off set into 50 ohm,
and a
-
120 mV offset open circuit.
The output signal from G6 is processed by the
the Q output of FF4 to change states. Flip-flop FF4
is reset by A5 to produce a nominally 5-ns wide