Service manual

Another important use of the 584 is timing with especially those with large volume, involves several

HPGe detectors. ln this application, the constant- interactive parameters. Refer to Section 6, Typical

fraction shaping delay selected is less than the Applications, and refs. 1 and 2 in Section 6.5.

minimum signal rise time. Depending on the size

and shape of the HPGe detector, the rise time can Other important uses of the 584 involve surface

range from 50 to 400 ns. A typical optimal constant- barrier detectors, Nal (TI) scintillators, microchannel

fraction shaping delay can range from 10 to 30 ns plates, laser diodes, and other time pick-off

with 20 ns a reasonable first choice. An ORTEC applications (Section 6). Contact your local

425A Nanosecond Delay can be used to adjust the ORTEC representative for the latest information on

shaping delay. Timing with HPGe detectors, state-of-the-art timing applications.

4. OPERATING INSTRUCTIONS

The 584 accepts negative input signals in the range An SRT timing mode can be employed to ensure

of 0 to -5 V. For each input pulse that satisfies the that leading edge time walk is not introduced by the

584 logic criteria, four output logic pulses are leading edge discriminator. Leading edge timing

initiated simultaneously. Two timing output signals can occur for input signals with exceptionally long

are provided: these are negative NIM fast logic rise times and for amplitude-and-rise time

pulses that are nominally 5 ns wide. A positive slow compensated (ARC) timing with input signals that

NIM output is provided through a front panel exceed the threshold of interest by only a slight

connector. The front panel Blocking Output is a amount. ln the SRT mode, an input signal that does

negative current logic signal similar to a NIM fast not cross the lower level threshold before the

logic pulse but with a width that is set by the period constant fraction zero crossing time will not produce

of the internal blocking one-shot, and this is output signals.

variable from 10 ns to 1000 ns.

5. CIRCUIT DESCRIPTION

5.1. OVERVIEW

Figure 5.1 is a simplified block diagram of the

ORTEC 584 and can be used as a reference to Threshold control and can range from -5 mV to

describe its operation. -1 V. The reference level is buffered from LE by A1.

The 584 can be operated in three separate timing The input signal is attenuated by Rl and R2 and

modes that are selectable by a front panel locking delayed by the external CF Shaping Delay. The

toggle switch. These three timing modes are

Constant Fraction (CF), Slow Rise Time Reject

(SRT), and Leading Edge (LE). The initial circuit

description will only cover CF operation. All logic

functions are implemented using ECL components

A 0 to -5 V input starts at time zero and is applied

to the leading edge discriminator, LE. The

reference level for LE is set by the front panel

attenuation factor is approximately f 0.2. The

attenuated and delayed input signals are

differentially summed in the constant-fraction

amplifier, CFA. The resulting bipolar shaped signal

is fed to the zero crossing gate, G1. Note that the

CFA signal can produce an output from G1 only if

G1 is armed by the output signal from LE.