User manual

Chapter 3. Operation
32 ATLAS 800 Series Video Module User Manual 61200773L1-1A
PLL/FIFO Displays the Phase Lock Loop (PLL) and FIFO status.
C
ONFIGURATION
All of the following configurable parameters apply to the individual Video Module
DTE ports.
P
RT
Displays the port number.
P
ORT
N
AME
Accepts any alpha-numeric name up to 16 characters long, to uniquely identify
each DTE port on the Video Module.
C
LK
+/-
Controls the clock used by the ATLAS 800 Series to accept the transmit (TX) data
from the DTE. This is usually set to N
ORMAL
. If the interface cable is long, causing
a phase shift in the data, the clock can be set to INVERTED
. This switches the phase
of the clock, which compensates for a long cable.
D
ATA
Controls the inverting of the DTE data. This inversion can be useful when operat-
ing with a high-level data link control (HDLC) protocol (often used as a means to
ensure 1s density). Select either N
ORMAL
or I
NVERTED
. Data inversion configura-
tion must match on both ends of the circuit.
CTS
Determines the behavior of the Clear To Send (CTS) signal. If set to N
ORMAL
, CTS
will follow the value of Request To Send (RTS). If set to F
ORCED
O
N
, CTS will
always be asserted.
DCD
Determines the behavior of the Data Carrier Detect (DCD) signal, also called
RLSD on some interfaces. If set to N
ORMAL
, DCD will generally be asserted when
the interface is capable of passing data (consult the appropriate ATLAS 800 Series
User Manual for exact conditions.) If set to F
ORCED
O
N
, DCD will always be
asserted.
DSR
Determines the behavior of the Data Set Ready (DSR) signal. If set to N
ORMA
l,
DSR will generally be asserted when the interface is capable of passing data. If set
to F
ORCED
O
N
, DSR will always be asserted.
P
ORT
Indicates the operating port.
PLL/FIFO Displays the state of the PLL and FIFO systems.
L
OCK
PLL is locked (This is required to transfer data.)
RXE Receive data FIFO empty
RXF Receive data FIFO full
TXE Transmit data FIFO empty
TXF Transmit data FIFO full