User guide

Registers 27
3.5 INT_CSR: Interrupt Control and Status Register
The interrupt of cPCI/PCI/PCIe-7300A is controlled and status is
checked through this register.
Address: BASE + 0x0C
Attribute: READ/WRITE
Data Format:
AUXDI_EN (R/W)
X 0: Disable AUXDI0 interrupt
X 1: Interrupt CPU on falling edge of AUXDI0
T2_EN (R/W)
X 0: Disable Timer2 interrupt
X 1: Interrupt CPU on falling edge of Timer 2 output
AUXDI0_INT (R/W)
X 0: AUXDI does not generate interrupt
X 1: AUXDI interrupt occurred. Write “1” to clear
T2_INT (R/W)
X 0: Timer 2 does not generate interrupt
X 1: Timer 2 interrupt occurred. Write “1” to clear
Bit # 3-0 T2_INT AUXIO_INT T2_EN AUXDI0_EN
Bit # 7-4 - - Reserved Reserved
Bit # 31-8 Don’t Care