Express-HL User’s Manual Manual Revision: 2.
Revision History Revision Description Date By 2.00 Initial release 2014-01-20 JC 2.01 Add PCH HM86 for Celeron CPUs; update block diagram; correct max. memory (16GB); remove -20°C to 70°C SKU; add SMBus device addresses; correct XDP Debug Header location. 2014-04-22 JC 2.02 Update Core™ i7-4860EQ frequency 2014-06-26 JC 2.03 Add BIOS beep codes; correct PCIe Configuration Switch settings 2014-09-26 JC 2.
Preface Copyright 2014-15 ADLINK Technology, Inc. This document contains proprietary information protected by copyright. All rights are reserved. No part of this manual may be reproduced by any mechanical, electronic, or other means in any form without prior written permission of the manufacturer. Disclaimer The information in this document is subject to change without prior notice in order to improve reliability, design, and function and does not represent a commitment on the part of the manufacturer.
Table of Contents Revision History ............................................................................................................ 2 Preface............................................................................................................................ 3 1 Introduction ............................................................................................................ 6 2 Specifications ......................................................................................
5.1 6 Smart Embedded Management Agent (SEMA) ................................................ 40 Board Specific SEMA Functions ................................................................................................. 41 System Resources ................................................................................................. 43 6.1 System Memory Map................................................................................................................. 43 6.
1 Introduction The Express-HL is a COM Express® COM.0 R2.1 Type 6 module supporting the 64-bit 4th Generation Intel® Core™ i7/i5/3 processor with Intel® QM87 Chipset and 4th Generation Intel® Celeron® processor with Intel® HM86 Chipset. The Express-HL is specifically designed for customers who need high-level processing and graphics performance in a long product life solution.
2 Specifications 2.1 Core System ¾ CPU: 4th Generation Intel® Core™ and Celeron® Processors - 22nm (formerly known as "Haswell Platform") • • • • • • • • Intel® Core™ i7-4860EQ 1.8 GHz (3.2 GHz Turbo), 47W (4C/GT3) Intel® Core™ i7-4700EQ 2.4/1.7 GHz (3.4 GHz Turbo), 47/37W (4C/GT2) Intel® Core™ i5-4400E 2.7 GHz (3.3 GHz Turbo), 37W (2C/GT2) Intel® Core™ i5-4402E 1.6 GHz (2.7 GHz Turbo), 25W (2C/GT2) Intel® Core™ i3-4100E 2.4 GHz (no Turbo) 3MB, 37W (2C/GT2) Intel® Core™ i5-4102E 1.
2.4 Audio ¾ Integrated: Intel® HD Audio integrated in PCH QM87/QM86 ¾ Audio Codec: Realtek ALC886 on Express-BASE6 2.5 LAN ¾ Integrated: LAN MAC integrated in PCH QM87/HM86 ¾ Intel PHY: Intel® Ethernet Controller i217LM ¾ Interface: 10/100/1000 GbE connection 2.6 Multi I/O and Storage ¾ Integrated in Intel® QM87/HM86 Chipset ¾ USB ports: 2 ports USB 3.0 (USB0, 1) and 6 ports USB 2.0 (USB3, 4, 5, 6, 7) – HM86 ¾ ¾ 4 ports USB 3.0 (USB0,1,2,3) and 4 ports USB 2.
2.10 Power Specifications ¾ Power Modes: ¾ Standard Voltage Input: ATX = 12V±5% / 5Vsb ±5% or AT = 12V ±5% ¾ Wide Voltage Input: ¾ Power Management: ACPI 4.0 compliant, Smart Battery support ¾ Power States: supports C1-C6, S0, S1, S4, S3, S5, S5 ECO mode (Wake on USB S3/S4, WOL S3/S4/S5) 2.11 AT and ATX mode (AT mode start controlled by SEMA) ATX = 8.5~20 V / 5Vsb ±5% or AT = 8.
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3 Pinouts and Signal Descriptions 3.1 AB / CD Pin Definitions The Express-HL is a Type 6 module supporting USB3.0 and DDI channels on the CD connector All pins in the COM Express specification are described, including those not supported on the Express-HL.
Row A Row B Row C Row D Pin Name Pin Name Pin Name Pin Name A36 USB6- B36 USB7- C36 DDI3_CTRLCLK_AUX+ D36 DDI1_PAIR3+ A37 USB6+ B37 USB7+ C37 DDI3_CTRLDATA_AUX- D37 DDI1_PAIR3- A38 USB_6_7_OC# B38 USB_4_5_OC# C38 DDI3_DDC_AUX_SEL D38 RSVD A39 USB4- B39 USB5- C39 DDI3_PAIR0+ D39 DDI2_PAIR0+ A40 USB4+ B40 USB5+ C40 DDI3_PAIR0- D40 DDI2_PAIR0- A41 GND (FIXED) B41 GND (FIXED) C41 GND (FIXED) D41 GND (FIXED) A42 USB2- B42 USB3- C42 DDI3_PAIR1+ D42
Row A Row B Row C Row D Pin Name Pin Name Pin Name Pin Name A81 LVDS_A_CK+ B81 LVDS_B_CK+ C81 PEG_RX9+ D81 PEG_TX9+ A82 LVDS_A_CK- B82 LVDS_B_CK- C82 PEG_RX9- D82 PEG_TX9- A83 LVDS_I2C_CK B83 LVDS_BKLT_CTRL C83 TPM_PP D83 RSVD A84 LVDS_I2C_DAT B84 VCC_5V_SBY C84 GND D84 GND A85 GPI3 B85 VCC_5V_SBY C85 PEG_RX10+ D85 PEG_TX10+ A86 RSVD B86 VCC_5V_SBY C86 PEG_RX10- D86 PEG_TX10- A87 RSVD B87 VCC_5V_SBY C87 GND D87 GND A88 PCIE0_CK_REF+ B88
3.2 Signal Description Terminology The following terms are used in the COM Express AB/CD Signal Descriptions below. I Input to the Module O Output from the Module I/O Bi-directional input / output signal OD Open drain output I 3.3V Input 3.3V tolerant I 5V Input 5V tolerant O 3.3V Output 3.3V signal level O 5V Output 5V signal level I/O 3.3V Bi-directional signal 3.3V tolerant I/O 5V Bi-directional signal 5V tolerant I/O 3.3Vsb Input 3.
3.3 AB Signal Descriptions 3.3.1 Audio Signals Signal Pin # Description I/O AC_RST# / HDA_RST# A30 Reset output to codec, active low. O 3.3VSB AC_SYNC / HDA_SYNC A29 Sample-synchronization signal to the codec(s). O 3.3V AC_BITCLK / HDA_BITCLK A32 Serial data clock generated by the external codec(s). I/O 3.3V AC _SDOUT / HDA_SDOUT A33 Serial TDM data output to the codec. O 3.3V AC _SDIN[2:0] HDA_SDIN[2:0] B28 B30 Serial TDM data inputs from up to 3 codecs. I/O 3.3V 3.3.
3.3.
3.3.5 Serial ATA Signal Pin # Description I/O SATA0_TX+ SATA0_TX- A16 A17 Serial ATA channel 0, Transmit Output differential pair. O SATA AC coupled on Module SATA0_RX+ SATA0_RX- A19 A20 Serial ATA channel 0, Receive Input differential pair. I SATA AC coupled on Module SATA1_TX+ SATA1_TX- B16 B17 Serial ATA channel 1, Transmit Output differential pair. O SATA AC coupled on Module SATA1_RX+ SATA1_RX- B19 B20 Serial ATA channel 1, Receive Input differential pair.
3.3.6 PCI Express Signal Pin # Description I/O PCIE_TX0+ PCIE_TX0- A68 A69 PCI Express channel 0, Transmit Output differential pair. O PCIE AC coupled on Module PCIE_RX0+ PCIE_RX0- B68 B69 PCI Express channel 0, Receive Input differential pair. I PCIE AC coupled off Module PCIE_TX1+ PCIE_TX1- A64 A65 PCI Express channel 1, Transmit Output differential pair. O PCIE AC coupled on Module PCIE_RX1+ PCIE_RX1- B64 B65 PCI Express channel 1, Receive Input differential pair.
3.3.9 USB Signal Pin # Description I/O USB0+ USB0- A46 A45 USB differential data pairs for Port 0 I/O 3.3VSB USB 1.1/ 2.0 compliant USB1+ USB1- B46 B45 USB differential data pairs for Port 1 I/O 3.3VSB USB 1.1/ 2.0 compliant USB2+ USB2- A43 A42 USB differential data pairs for Port 1 I/O 3.3VSB USB 1.1/ 2.0 compliant USB3+ USB3- B43 B42 USB differential data pairs for Port 2 I/O 3.3VSB USB 1.1/ 2.0 compliant USB4+ USB4- A40 A39 USB differential data pairs for Port 3 I/O 3.
3.3.
3.3.11 SPI (BIOS only) Signal Pin # Description I/O PU/PD SPI_CS# B97 Chip select for Carrier Board SPI BIOS Flash. O 3.3VSB PU 10K 3.3VSB SPI_MISO A92 Data in to module from carrier board SPI BIOS flash. I 3.3VSB SPI_MOSI A95 Data out from module to carrier board SPI BIOS flash. O 3.3VSB SPI_CLK A94 Clock from module to carrier board SPI BIOS flash. O 3.3VSB SPI_POWER A91 Power supply for Carrier Board SPI – sourced from Module – nominally 3.3V.
3.3.14 I2C Bus Signal Pin # Description I/O PU/PD I2C_CK B33 General purpose I²C port clock output/input I/O OD 3.3VSB PU 2k2 3.3VSB I2C_DAT B34 General purpose I²C port data I/O line I/O OD 3.3VSB PU 2k2 3.3VSB 3.3.15 Comment General Purpose I/O (GPIO) Signal Pin # Description I/O PU/PD Comment GPO[0] A93 General purpose output pins. O 3.3V PU 10K 3.3V After hardware RESET output low GPO[1] B54 General purpose output pins. O 3.3V PU 10K 3.
3.3.17 Power And System Management Signal Pin # Description I/O PU/PD PWRBTN# B12 Power button to bring system out of S5 (soft off), active on falling edge. I 3.3VSB PU 10k 3.3VSB SYS_RESET# B49 Reset button input. Active low request for module to reset and reboot. May be falling edge sensitive. For situations when SYS_RESET# is not able to reestablish control of the system, PWR_OK or a power cycle may be used. I 3.3V PU 10k 3.3V CB_RESET# B50 Reset output from module to Carrier Board.
3.4 CD Signal Descriptions 3.4.1 USB 3.
3.4.3 DDI Channels DDI 1 Signal Pin Description I/O DDI1_PAIR0+ DDI1_PAIR0DDI1_PAIR1+ DDI1_PAIR1DDI1_PAIR2+ DDI1_PAIR2DDI1_PAIR3+ DDI1_PAIR3DDI1_PAIR4+ DDI1_PAIR4DDI1_PAIR5+ DDI1_PAIR5DDI1_PAIR6+ DDI1_PAIR6- D26 D27 D29 D30 D32 D33 D36 D37 C25 C26 C29 C30 C15 C16 Digital Display Interface1 differential pairs O PCIE DDI1_HPD C24 Digital Display Interface Hot-Plug Detect I PCIE DDI1_CTRLCLK_AUX+ D15 IF DDI1_DDC_AUX_SEL is floating I/O PCIe DP1_AUX+ IF DDI1_DDC_AUX_SEL pulled high I/O OD 3.
DDI 2 Signal Pin Description DDI2_PAIR0+ DDI2_PAIR0DDI2_PAIR1+ DDI2_PAIR1DDI2_PAIR2+ DDI2_PAIR2DDI2_PAIR3+ DDI2_PAIR3- D39 D40 D42 D43 D46 D47 D49 D50 Digital Display Interface2 differential pairs DDI2_HPD D44 DDI2_CTRLCLK_AUX+ C32 DDI2_CTRLCLK_AUX- DDI2_DDC_AUX_SEL C33 I/O PU/PD Comment PD 100K IF DDI2_DDC_AUX_SEL is floating I/O PCIe DP2_AUX+ IF DDI2_DDC_AUX_SEL pulled high I/O OD 3.
3.4.
3.4.
Signal Pin PEG_TX15+ PEG_TX15- D101 D102 PEG_LANE_RV# D54 3.4.6 Description I/O PU/PD Comment AC coupled on Module PCI Express Graphics lane reversal input strap. Pull low on the Carrier board to reverse lane order. I 3.3V PU 10K 3.3V Module Type Definition Signal Pin # Description I/O TYPE0# TYPE1# TYPE2# C54 C57 D57 The TYPE pins indicate to the Carrier Board the Pin-out Type that is implemented on the module.
4 Connector Pinouts on Module This chapter describes connectors and pinouts, LEDs and switches that are used on the module but are not included in the PICMG standard specification ¾ Connector and LED Locations XDP 60-pin to CPU BIOS Defaults RESET Button CD AB FAN 4-pin FAN Express-HL 40-pin Debug connector Page 31
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40-pin Pin Description on the COM Express Module ¾ Pin Interface Signal Remark Pin Interface Signal 1 SPI Program interface VCC_SPI_IN SPI Power Input from flash tool to module.
4.2 Status LEDs To facilitate easier maintenance, status LED’s are mounted on the board. ¾ LED Descriptions Name Color Connection Function LED1 Blue BMC output Power Sequence Status Code (BMC) Power Changes, RESET (see 5.1.
4.3 XDP Debug Header The debug port is a connection into a target-system environment that provides access to JTAG, run control, system control, and observation resources. The XDP target system connector is a Samtec™ 60-pin BSH-030-01 series connector.
4.4 Fan Connector ¾ Connector Type: JVE 24W1125A-04M00 ¾ Pin Assignment Name Signal Description 1 BMC_FAN_OUT FAN_PWMOUT 2 BMC_FAN_PWM_IN FAN_TACHIN 3 GND Ground 4 P5V_S 5V 4.5 BIOS Setup Defaults RESET Button To perform a hardware reset of BIOS default settings, perform the following steps: 1. Shut down the system. 2. Press the BIOS Setup Defaults RESET Button continuously and boot up the system. You can release the button when the BIOS prompt screen appears 3.
4.6 Express-HL Switch Settings 4.6.
4.6.2 SW1: PCI Express Configuration Switch Switch SW1 allows you to configure the PCI Express x16 lanes from the CPU as 1 PCIe x16, 2 PCIe x8, or 1 PCIe x8 + 2 PCIe x4. Mode 4.6.3 Pin 1 Pin 2 1x PCIe x16 (default) Off Off 2x PCIe x8 On Off 1x PCIe x8 + 2x PCIe x4 On On Reserved Off On SW4: LVDS Panel Configuration Switch Switch SW4 allows you to set the LVDS panel mode to 18-bit or 24-bit. Mode 4.6.
4.7 PCIe x16-to-two-x8 Adapter Card The Express-HL can be used with the PCIe x16-to-two-x8 Adapter Card on the Express-BASE6 Reference Carrier to support bifurbication of the CPU's PEG interface (PCIe x16). The card reroutes the PCIe x16 to two x8 and allows testing of two independent PCIe add-on cards with x8/x4/x2/x1 width. To use the card, set SW1 to "2 x8 PCI Express" as above. PCIex16-to-two-x8 Adapter Card (Model: P16TO28, Part No.
5 Smart Embedded Management Agent (SEMA) The onboard microcontroller (BMC) implements power sequencing and Smart Embedded Management Agent (SEMA) functionality. The microcontroller communicates via the System Management Bus with the CPU/chipset. The following functions are implemented: • Total operating hours counter. Counts the number of hours the module has been run in minutes. • On-time minutes counter. Counts the seconds since last system start.
5.1 Board Specific SEMA Functions 5.1.1 Voltages The BMC of the Express-HL implements a voltage monitor and samples several onboard voltages. The voltages can be read by calling the SEMA function “Get Voltages”. The function returns a 16-bit value divided into high-byte (MSB) and low-byte (LSB). 5.1.2 ADC Channel Voltage Name Voltage Formula [V] 0 --- --- 1 +V3.3S (MSB<<8 + LSB) x 1.100 x 3.3 / 1024 2 +V1.05S (MSB<<8 + LSB) x 3.3 / 1024 3 +V3.3A (MSB<<8 + LSB) x 1.100 x 3.
5.1.4 Exception Codes In case of an error, the BMC drives a blinking code on the blue Status LED (LED1). The same error code is also reported by the BMC Flags register. The Exception Code is not stored in the Flash Storage and is cleared when the power is removed. Therefore, a “Clear Exception Code” command is not needed or supported. 5.1.
6 System Resources 6.1 System Memory Map Address Range (decimal) Address Range (hex) Size Description (4GB-2MB) FFE00000 – FFFFFFFF 2 MB High BIOS Area (4GB-18MB) – (4GB-17MB-1) FEE00000 – FEEFFFFF 1 MB MSI Interrupts (4GB-20MB) – (4GB-19MB-1) FEC00000 – FECFFFFF 1 MB APIC Configuration Space 15MB – 16MB F00000 – FFFFFF 1 MB ISA Hole 1MB -15MB 100000 - EFFFFF 14MB Main Memory 0K –1MB 00000 – FFFFFF 1MB DOS Compatibility Memory 6.
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I/O Map (cont'd) Hex Range Device 3BC-3BE Reserved for parallel port 3C0-3DF VGA registers 3E0-3EF Available 3F0-3F7 Available 3F8-3FF Serial port 1 4D0 Master PIC Edge/Level Trigger register 4D1 Slave PIC Edge/Level Trigger register CF8-CFB PCI configuration address register (32 bit I/O only) CF9 Reset Control register (8 bit I/O) CFC-CFF PCI configuration data register 580 Smbus base address for SB.
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APIC Mode (cont'd) IRQ# Typical Intterupt Resource Connected to Pin Available 16 N/A Intel HDA, PCIE Port 0/1/2/3/4/5/6, EHCI Conterller #2 ,P.E.G Root Port, I.G.D ,XHCI Controller Note (1) 17 N/A PCIE Port 0/1/2/3/4/5/6, P.E.G Root Port, Note (1) 18 N/A PCIE Port 0/1/2/3/4/5/6, P.E.G Root Port, SMBus Controller, EHCI Controller #2 Note (1) 19 N/A PCIE Port 0/1/2/3/4/5/6, P.E.
6.5 PCI Configuration Space Map Bus Number Device Number Function Number Routing Description 00h 00h 00h N/A Intel host Bridge 00h 02h 00h Internal Intel I.G.
6.6 PCI Interrupt Routing Map INT Line P.E.
7 BIOS Setup 7.1 Menu Structure This section presents the six primary menus of the BIOS Setup Utility. Use the following table as a quick reference for the contents of the BIOS Setup Utility. The subsections in this section describe the submenus and setting options for each menu item. The default setting options are presented in bold, and the function of each setting is described in the right hand column of the respective table.
7.2 Main The Main Menu provides read-only information about your system and also allows you to set the System Date and Time. Refer to the tables below the screen shot of this menu for details of the submenus and settings. 7.2.1 System Information Feature Options Description BIOS Version Info only ADLINK BIOS version. Board Revision Info only Hardware revision. Build Date and Time Info only ADLINK date the BIOS was build. 7.2.
7.2.3.1 PCH Information System Management Feature Options System Management Info only Version 7.2.4 Description Info only Display version. System Management 7.2.4.1 System Management > Board Information Board Information Info only SMC Firmware Read only Display SMC Firmware. Build Date Read only Display SMC firmware build date. SMC Boot loader Read only Display SMC boot loader. Build Date Read only Display SMC boot loader build date.
7.2.4.3 System Management > Power Consumption Feature Options Power Consumption Info only Description Current Input Current Read only Display input current. Current Input Power Read only Display input power. AIN0 Read only Display actual voltage of the AIN0. V3.30 Read only Display actual voltage of the V3.30. V1.05 Read only Display actual voltage of the V1.05. Vtt Read only Display actual voltage of the VTT. V1.35 Read only Display actual voltage of the V1.35. V5.
7.2.4.6 System Management > Power Up Feature Options Power Up Info only Power Up watchdog Attention: F12 disables the Power Up Watchdog. Enabled Disabled The Power-Up Watchdog resets the system after a certain amount of time after power-up. Disabled Enable Reduces the power consumption of the system. Turn on Remain off Last State Turn On: The machine starts automatically when the power supply is turned on. Remain Off :To start the machine the power button has to be pressed.
7.2.
7.3 Advanced This menu contains the settings for most of the user interfaces in the system 7.3.1 CPU Feature Options Description CPU Info only Manufacturer, model, speed CPU Signature Info only Display CPU Signature. Processor Family Info only Display Processor Family. Microcode Patch Info only Display Microcode Patch. Max CPU speed Info only Display Max CPU speed. Min CPU speed Info only Display Min CPU speed. CPU Speed Info only Display CPU Speed.
Feature Options Description CPU C3 Report Disabled Enabled Enable/Disable CPU C3 report to OS. CPU C6 Report Disabled Enabled Enable/Disable CPU C6 report to OS. CPU C7 Report Disabled CPU C7 CPU C7S Enable/Disable CPU C7 report to OS. ACPI T State Disabled Enabled Enable/Disable ACPI T state support. CPU DTS Disabled Enabled Enable/Disable CPU DTS. Feature Options Description Memory RC Version Info only Display Memory Reference Code Version.
7.3.3 Graphics Feature Options Graphics Configuration Info only IGFX VBIOS Version Info only Display VBIOS Version. IGfx Frequency Info only Display IGfx Frequency. Graphics Turbo IMON Current Number entry field Graphics turbo IMON current values supported (14-31). Primary Display Auto IGFX PEG PCIE Select which of IGFX/PEG/PCI Graphics device should be Primary Display Or select SG for Switchable Gfx.
Feature Options Description LCD Panel Type VBIOS Default 640X480 800X600 1024X768 1280X1024 1400X1050 1600X1200 1366X768 1680X1050 1920X1200 1440X900 1600X900 1024X768 LVDS2 1280X800 1920X1080 2048X1536 Select LCD panel used by Internal Graphics Device by selecting the appropriate setup item. Active LFP No LVDS Edp Port-A Select the Active LFP Configuration.
Feature Options Software Feature Mask Configuration Info only RAID0 Enabled Disabled Enable/Disable RAID0 feature. RAID1 Enabled Disabled Enable/Disable RAID1 feature. RAID10 Enabled Disabled Enable/Disable RAID10 feature. RAID5 Enabled Disabled Enable/Disable RAID5 feature. Intel Rapid Recovery Technology Enabled Disabled Enable/Disable Intel Rapid Recovery Technology. OROM UI and BANNER Enabled Disabled If enabled, then the OROM UI is shown.
Feature Options Description Hot Plug Disabled Enabled Designates this port as Hot Pluggable. Mechanical Presence Disabled Enabled Controls reporting if this port has an Mechanical Presence Switch.\n\nNote: Requires hardware support. External SATA Disabled Enabled External SATA Support. SATA Device Type Hard Disk Drive Sold State Drive Identify the SATA port is connected to Solid State Drive or Hard Disk Drive.
7.3.5.1 USB > PCH USB Configuration Feature Options Description USB Precondition Disabled Enabled Precondition work on USB host controller and root ports for faster enumeration. XHCI Mode Disabled Enabled Mode of operation of xHCI controller. BTCG Disabled Enable Enable/Disable trunk clock gating. USB Precondition Disabled Enabled Precondition work on USB host controller and root ports for faster enumeration. USB Port #0~13 Disabled Enabled Control each of the USB ports (0~13) disabling.
Feature Options Description PET Progress Enabled Disabled User can Enable/Disable PET Events progress to recieve PET events or not. AMT CIRA Timeout 0 OEM defined timeout for MPS connection to be established. 0 - use the default timeout value of 60 seconds. 255 - MEBX waits until the connection succeeds. Watchdog Enabled Disabled Enable/Disable WatchDog Timer. OS Timer Set OS watchdog timer. BIOS Timer Set BIOS watchdog timer. 7.3.
Feature Options Description Extended Synch Enabled Disabled If enabled the generation of PCI Express synchronization patterns is allowed Link Training Retry Disabled 2 3 5 Defines number of Retry Attempts software will take to retrain the link if previous training attempt was unsuccessful. Link Training Timeout (uS) 100 Defines number of microseconds software will wait before polling 'Link Training' bit in Link Status register. Value range from 10 to 10000 uS.
Feature Options Description Disable PEG RxCEM LoopBack Mode Disabled Enable Enabled/Disabled PEG RxCEM Loopback Mode. PCIe Gen3 RxCTLEp Setting 0~7 8 The range of the setting is (0~15) This setting has to be specified basing on platform design and following the guideline. 7.3.7.2 PCI and PCIe > PCH-PCIe Configuration Feature Options PCH-PCIe Configuration Info only Description PCI Express Clock Gating Disabled Enable Enable/Disable PCI Express Clock Gating for each root port.
Feature 7.3.8 Options Description CER Disabled Enable Enable/Disable PCI Express Device Correctable Error Reporting. CTO Disabled Enable Enable/Disable PCI Express Completion Timer TO. SEFE Disabled Enable Enable/Disable Root PCI Express System Error on Fatal Error. SENFE Disabled Enable Enable/Disable Root PCI Express System Error on NonFatal Error. SECE Disabled Enable Enable/Disable Root PCI Express System Error on Correctable Error.
Feature Change Settings Serial Port 2 Configuration Serial Port Options Auto IO=3F8h; IRQ=4 IO=3F8h; IRQ=3,4,5,6,7,10,11,12 IO=2F8h; IRQ=3,4,5,6,7,10,11,12 IO=3E8h; IRQ=3,4,5,6,7,10,11,12 IO=2E8h; IRQ=3,4,5,6,7,10,11,12 Description Select an optimal setting for Super IO device. Enabled Disabled Enable/Disable Serial Port (COM). Device Settings IO=2F8h; IRQ=4 Fixed configuration of serial port.
7.3.9 ACPI and Power Management Feature Options ACPI and Power Management Info only Enable ACPI Auto Configuration Enabled Disabled Enables or Disables BIOS ACPI Auto Configuration. Enable Hibernation Enabled Disabled Enables or Disables System ability to Hibernate (OS/S4 Sleep State). This option may be not effective with some OS. ACPI Sleep State S3 only Select ACPI sleep state the system will enter when the SUSPEND button is pressed.
7.3.11.1 Serial Port Console > Console Redirection Settings Feature Options Console Redirection Settings Info only Terminal Type VT100 VT100+ VT-UTF8 ANSI Emulation: ANSI: Extended ASCII char set. VT100: ASCII char set. VT100+: Extends VT100 to support color, function keys, etc. VT-UTF8: Uses UTF8 encoding to map Unicode chars onto 1 or more bytes. Bits per second 9600 19200 38400 57600 115200 Selects serial port transmission speed. Data Bits 7 8 Select Data Bits.
Feature Options Description Turn off unused PCI/PCIe clocks Disabled Enable Disabled: all clocks turned on. Enabled: clocks for empty PCI/PCIe slots will be turned off to save power. Platform must be powered off for changes to take effect. ICC Locks After EOP Default All Locked All UnLocked Lock ICC register after EOP. Clock Manipulation Info only ICC Overclocking Lib Info only CLKRUN# Logic Enabled Disabled Enable the CLKRUN# logic to stop the PCI clock.
Feature Options Trusted Computing Submenu Intel TXT(LT) Configuration Enabled Disabled 7.3.14.1 Description Enables or Disables the High Precision Event Timer.
7.4 Boot 7.4.1 Boot Configuration Feature Options Description Boot Configuration Info only Setup Prompt Timeout 1 Enable/Disable the onboard SATA controllers. Bootup NumLock State On Select SATA controller mode. Quiet Boot Disabled Enabled Enable/Disable the PATA port. In fact this enables or disables the SATA channel on which the onboard SATA to PATA converter is attached.
7.5 Security 7.5.1 Password Description Feature Options Administrator Password Enter password User Password Enter password Secure Boot menu Submenu 7.5.2 Description Secure Boot Menu Feature Options Description System Mode Setup Secure Boot Info only Secure Boot Support Disabled Enabled Secure Boot can be enabled if 1.System running in User mode with enrolled Platform Key(PK) 2.CSM function is disabled. Secure Boot Mode Standard Custom Secure Boot mode selector.
8 BIOS Checkpoints, Beep Codes This section of this document lists checkpoints and beep codes generated by AMI Aptio BIOS. The checkpoints defined in this document are inherent to the AMIBIOS generic core, and do not include any chipset or board specific checkpoint definitions. Checkpoints and Beep Codes Definition A checkpoint is either a byte or word value output to I/O port 80h.
8.1 Status Code Ranges Status Code Range Description 0x01 – 0x0F SEC Status Codes & Errors 0x10 – 0x2F PEI execution up to and including memory detection 0x30 – 0x4F PEI execution after memory detection 0x50 – 0x5F PEI errors 0x60 – 0xCF DXE execution up to BDS 0xD0 – 0xDF DXE errors 0xE0 – 0xE8 S3 Resume (PEI) 0xE9 – 0xEF S3 Resume errors (PEI) 0xF0 – 0xF8 Recovery (PEI) 0xF9 – 0xFF Recovery errors (PEI) 8.2 Standard Status Codes 8.2.
8.2.2 SEC Beep Codes None 8.2.
Status Code Description 0x4F DXE IPL is started PEI Error Codes 0x50 Memory initialization error. Invalid memory type or incompatible memory speed 0x51 Memory initialization error. SPD reading has failed 0x52 Memory initialization error. Invalid memory size or memory modules do not match. 0x53 Memory initialization error. No usable memory detected 0x54 Unspecified memory initialization error.
8.2.4 PEI Beep Codes # of Beeps Description 1 Memory not Installed 1 Memory was installed twice (InstallPeiMemory routine in PEI Core called twice) 2 Recovery started 3 DXEIPL was not found 3 DXE Core Firmware Volume was not found 7 Reset PPI is not available 4 Recovery failed 4 S3 Resume failed 8.2.
Status Code Description 0x77 South Bridge DXE Initialization (South Bridge module specific) 0x78 ACPI module initialization 0x79 CSM initialization 0x7A – 0x7F Reserved for future AMI DXE codes 0x80 – 0x8F OEM DXE initialization codes 0x90 Boot Device Selection (BDS) phase is started 0x91 Driver connecting is started 0x92 PCI Bus initialization is started 0x93 PCI Bus Hot Plug Controller Initialization 0x94 PCI Bus Enumeration 0x95 PCI Bus Request Resources 0x96 PCI Bus Assign Resou
Status Code Description 0xAF Exit Boot Services event 0xB0 Runtime Set Virtual Address MAP Begin 0xB1 Runtime Set Virtual Address MAP End 0xB2 Legacy Option ROM Initialization 0xB3 System Reset 0xB4 USB hot plug 0xB5 PCI bus hot plug 0xB6 Clean-up of NVRAM 0xB7 Configuration Reset (reset of NVRAM settings) 0xB8 – 0xBF Reserved for future AMI codes 0xC0 – 0xCF OEM BDS initialization codes DXE Error Codes 0xD0 CPU initialization error 0xD1 North Bridge initialization error 0xD2 So
8.2.7 ACPI/ASL Checkpoint Status Code Description 0x01 System is entering S1 sleep state 0x02 System is entering S2 sleep state 0x03 System is entering S3 sleep state 0x04 System is entering S4 sleep state 0x05 System is entering S5 sleep state 0x10 System is waking up from the S1 sleep state 0x20 System is waking up from the S2 sleep state 0x30 System is waking up from the S3 sleep state 0x40 System is waking up from the S4 sleep state 0xAC System has transitioned into ACPI mode.
9 Mechanical Information 9.1 Board-to-Board Connectors To allow for different stacking heights, the receptacles for COM Express carrier boards are available in two heights: 5 mm and 8 mm. When 5 mm receptacles are chosen, the carrier board should be free of components. Tyco 3-1827253-6 Foxconn QT002206-2131-3H • 220-pin board-to-board connector with 0.5mm for a stacking height of 5 mm. • This connector can be used with 5 mm through-hole standoffs (SMT type).
9.2 Thermal Solution 9.2.1 Heat Spreaders The function of the heat spreader is to ensure an identical mechanical profile for all COM Express modules. By using a heat spreader, the thermal solution that is built on top of the module is compatible with all COM Express modules. 9.2.2 Heat Sinks A heat sink can be used as a thermal solution for a specific COM Express module and can have a fan or be fanless, depending on the thermal requirements. 9.2.
Step 4: Use the four M2.5, L=6mm screws provided to fasten the heatsink to the module. Step 5: Place the COM Express module and heatsink assembly onto the connectors on the carrier board as shown. Then press down on the module until it is firmly seated on the carrier board. Step 6: Use the five M2.5, L=16mm screws provided to secure the COM Express module to the carrier board from the solder side. Step 7: If you are installing a heatsink with a fan, plug the fan connector into the carrier board as shown.
9.3 Mounting Methods There are several standard ways to mount the COM Express module with a thermal solution onto a carrier board. In addition to the choice of 5 mm or 8mm board-to-board connectors, there is the choice of Top and Bottom mounting. In Top mounting, the threaded standoffs are on the carrier board and the thermal solution is equipped with through-hole standoffs. In Bottom mounting, the threaded standoffs are on the thermal solution and the carrier board has through-hole standoffs.
9.4 Standoff Types The standoffs available for Top and Bottom mounting methods are shown below. Note that threaded standoffs are DIP type and throughhole standoffs are SMT type. Other types not listed are available upon request.
Safety Instructions Read and follow all instructions marked on the product and in the documentation before you operate your system. Retain all safety and operating instructions for future use. • Please read these safety instructions carefully. • Please keep this User‘s Manual for later reference. • Read the specifications section of this manual for detailed information on the operating environment of this equipment.
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