NuDAQ / NuIPC PCI-7200 / cPCI-7200 / LPCI-7200S 12MB/S High Speed Digital I/ O Card User’s Manual Manual Rev. 2.00 Revision Date: March 31, 2006 Part No: 50-11102-1030 Advance Technologies; Automate the World.
Copyright 2006 ADLINK TECHNOLOGY INC. All Rights Reserved. The information in this document is subject to change without prior notice in order to improve reliability, design, and function and does not represent a commitment on the part of the manufacturer. In no event will the manufacturer be liable for direct, indirect, special, incidental, or consequential damages arising out of the use or inability to use the product or documentation, even if advised of the possibility of such damages.
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Table of Contents Table of Contents..................................................................... i List of Tables.......................................................................... vi List of Figures ....................................................................... vii 1 Introduction ........................................................................ 1 1.1 1.2 1.3 1.4 Applications ......................................................................... 1 Features.................
3.3 3.4 3.5 3.6 Digital Output Register (BASE + 14).................................. DIO Status & Control Register (BASE + 18)...................... Interrupt Status & Control Register (BASE + 1C) .............. 8254 Timer Registers (BASE + 0) ..................................... 26 26 29 32 4 Operation Theory .............................................................. 33 4.1 4.2 4.3 4.4 4.5 Direct Program Control ...................................................... Timer Pacer Mode .............
5.8 5.9 5.10 5.11 5.12 5.13 5.14 5.15 @ Argument ................................................................. 49 @ Return Code ............................................................. 49 _7200_AUX_DO_Channel................................................. 50 @ Description ............................................................... 50 @ Syntax ...................................................................... 50 @ Argument ...........................................................
5.16 5.17 5.18 5.19 5.20 5.21 5.22 5.23 iv @ Argument .................................................................. 58 @ Return Code ............................................................. 58 _7200_Free_DBDMA_Mem............................................... 59 @ Description ............................................................... 59 @ Syntax ...................................................................... 59 @ Argument ......................................................
5.24 5.25 5.26 5.27 5.28 @ Argument ................................................................. 69 @ Return Code ............................................................. 69 _7200_DO_DMA_Start...................................................... 70 @ Description ............................................................... 70 @ Syntax ...................................................................... 70 @ Argument .................................................................
List of Tables Table 2-1: CN1A Pin Assignments .......................................... 19 Table 2-2: CN1B Pin Assignments .......................................... 20 Table 2-3: Pull-ups and termination of PCI/cPCI-7200 and LPCI7200S. .................................................................... 22 Table 5-1: Data Types .............................................................
List of Figures Figure 2-1: Figure 2-2: Figure 2-3: Figure 2-4: Figure 2-5: Figure 2-6: Figure 2-7: Figure 2-8: Figure 2-9: PCI-7200 Layout Diagram ....................................... 11 cPCI-7200 Layout Diagram ..................................... 12 LPCI-7200S Layout Diagram................................... 13 LPCI-7200S with standard PCI bracket................... 14 CN1 Pin Assignments.............................................. 17 CN2 Pin Assignments...........................................
1 Introduction The PCI-7200, cPCI-7200, and LPCI-7200S are PCI/CompactPCI/ Low profile PCI form factor high-speed digital I/O cards, consisting of 32 digital input channels, and 32 digital output channels. High performance design and state-of-the-art technology make this card suitable for high-speed digital input and output applications. The PCI-7200 performs high-speed data transfers using bus-mastering DMA via the 32-bit PCI bus architecture.
1.
1.
Programmable Counter X Device: 82C54-10, with a 4MHz time base X Timer 0: DI clock source X Timer 1: DO clock source X Timer2: Base clock of Timer #0 and Timer #1 X Pacer Output: 0.
1.4 Supporting Software ADLINK provides versatile software drivers and packages for users’ different approach to building a system. We not only provide programming library for many Windows systems, but also provide drivers for many software packages including LabVIEW®, HP VEETM, DASYLabTM, InTouchTM, InControlTM, ISaGRAFTM, etc. All software options are included in the ADLINK CD. Commercial software drivers require licenses.
DAQ-LVIEW PnP: LabVIEW® Driver DAQ-LVIEW PnP contains the VIs, which are used to interface with NI’s LabVIEW® software package. The DAQ-LVIEW PnPW supports Windows 98/NT/2000/XP. The LabVIEW® drivers are shipped free of charge with the board. These can be installed and used without license. For further detailed information about DAQLVIEW PnP, please refer to the user’s guide in the CD.
server is included on the ADLINK CD. It requires a license. The DDE server can be used in conjunction with any DDE client under Windows NT. PCIS-ISG: ISaGRAFTM driver The ISaGRAF WorkBench is an IEC1131-3 SoftPLC control program development environment. The PCIS-ISG includes ADLINK products’ target drivers for ISaGRAF under the Windows NT environment. The PCIS-ISG is included on the ADLINK CD. It requires a license.
8 Introduction
2 Installation This chapter describes how to install the PCI-7200. Package contents and unpacking information are described. Because the PCI7200 is a Plug and Play device, there are no jumper or DIP switch settings for configuration. The interrupt number and I/O port address are assigned by the system BIOS during system boot up. 2.
2.2 Unpacking The PCI-7200 card contains sensitive electronic components that can be easily damaged by static electricity. The work area should have a grounded anti-static mat. The operator should be wearing an anti-static wristband, grounded at the same point as the anti-static mat. Inspect the card module carton for obvious damage. Shipping and handling may cause damage to the module. Ensure there is no shipping and handling damage on the module before proceeding.
2.
Figure 2-2: cPCI-7200 Layout Diagram 12 Installation
Figure 2-3: LPCI-7200S Layout Diagram Installation 13
Figure 2-4: LPCI-7200S with standard PCI bracket 14 Installation
2.5 Hardware Installation Outline Hardware configuration These PCI cards (or CompactPCI, Low Profile PCI cards) are equipped with a Plug and Play PCI controller that requests base addresses and interrupts according to PCI standard. The system BIOS will install the system resource based on the PCI cards’ configuration registers and system parameters (which are set by system BIOS). Interrupt assignment and memory usage (I/O port locations) of the PCI cards can be assigned by system BIOS only.
2.6 Connector Pin Assignments PCI-7200 Pin Assignments The PCI-7200 comes equipped with one 37-pin D-Sub connector (CN2) located on the rear mounting plate and one 40-pin female flat cable header connector (CN1). The CN2 is located on the rear mounting plate; the CN1 is on front of the board. Refer section 2.4 PCI-7200‘s layout. CN2 is used for digital inputs (DI 0 to DI 15) and digital outputs (DO 0 to DO 15) The reminding digital I/O channels DI 16 to DI 31 and DO 16 to DO 31 are on CN1.
DI16 DI17 DI18 DI19 DI20 DI21 DI22 DI23 DI24 DI25 DI26 DI27 DI28 DI29 DI30 DI31 +5V O_ACK O_REQ N/C 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 DO16 DO17 DO18 DO19 DO20 DO21 DO22 DO23 DO24 DO25 DO26 DO27 DO28 DO29 DO30 DO31 GND O_TR1 N/C N/C Figure 2-5: CN1 Pin Assignments DI 0 DI 1 DI 2 DI 3 DI 4 DI 5 DI 6 DI 7 DI 8 DI 9 DI10 DI11 DI12 DI13 DI14 DI15 +5V 1 I_ACK I_REQ 18 2 3 4 5 6 7 8 9 10 11 1
cPCI-7200 Pin Assignments Figure 2-7: CN Pin Assignments 18 Installation
LPCI-7200S Pin Assignments DIN0 A1 A35 GND DIN1 A2 A36 GND DIN2 A3 A37 GND DIN3 A4 A38 GND DIN4 A5 A39 GND DIN5 A6 A40 GND DIN6 A7 A41 GND DIN7 A8 A42 GND DIN8 A9 A43 GND DIN9 A10 A44 GND DIN10 A11 A45 GND DIN11 A12 A46 GND DIN12 A13 A47 GND DIN13 A14 A48 GND DIN14 A15 A49 GND DIN15 A16 A50 GND DIN16 A17 A51 GND DIN17 A18 A52 GND DIN18 A19 A53 GND DIN19 A20 A54 GND DIN20 A21 A55 GND DIN21 A22 A56 GND DIN22 A23 A57 GND DIN23 A24
DOUT0 B1 B35 GND DOUT1 B2 B36 GND DOUT2 B3 B37 GND DOUT3 B4 B38 GND DOUT4 B5 B39 GND DOUT5 B6 B40 GND DOUT6 B7 B41 GND DOUT7 B8 B42 GND DOUT8 B9 B43 GND DOUT9 B10 B44 GND DOUT10 B11 B45 GND DOUT11 B12 B46 GND DOUT12 B13 B47 GND DOUT13 B14 B48 GND DOUT14 B15 B49 GND DOUT15 B16 B50 GND DOUT16 B17 B51 GND DOUT17 B18 B52 GND DOUT18 B19 B53 GND DOUT19 B20 B54 GND DOUT20 B21 B55 GND DOUT21 B22 B56 GND DOUT22 B23 B57 GND DOUT23 B24 B58 GND DOUT24 B
2.7 8254 for Timer Pacer Generation 8254 Timer/Counter “H” “H” CLK0 GATE0 CLK1 GATE1 4MHz Clock Timer 0 OUT0 Digital Input Timer Pacer OUT1 Digital Output Timer Pacer Timer 1 Timer 2 “H” CLK2 GATE2 OUT2 Figure 2-8: 8254 configuration The internal timer/counter 8254 on the PCI-7200 is configured as the above diagram (Figure 2.7). Users can use it to generate the timer pacer for both digital input and digital output triggers.
2.8 LPCI-7200S PCI Bus Signaling Low-Profile PCI is a new PCI card standard for space-constrained system designs. The new form factor has the same electrical protocols, PCI signals, and software drivers as standard PCI v2.2 expansion cards. However, the Low-Profile PCI bus interface only supports 3.3V signaling. To support both 5V and 3.3V signaling, LPCI-7200S implements 5V I/O tolerant bus switches to achieve the I/O voltage transition. This allows LPCI-7200S to be used in both 5V and 3.3V systems. 2.
Figure 2-9: Digital input pull-up resistor and termination circuit diagram.
24 Installation
3 Register Format 3.1 I/O Registers Format The PCI-7200 occupies eight consecutive 32-bit I/O addresses in the PC I/O address space. The cPCI-7200 occupies nine consecutive 32-bit I/O addresses. Table 4-1 shows the I/O Map. Address Read Write Base + 0 Counter 0 Counter 0 Base + 4 Counter 1 Counter 1 Base + 8 Counter 2 Counter 2 Base + C --- CLK Control CW0 Base + 10 Digital Input Reg. --- Base + 14 Digital Output (Read-back) Digital Output Reg.
3.3 Digital Output Register (BASE + 14) 32 digital output channels can be written and read to/from this register Address: BASE + 14 Attribute: READ/WRITE Data Format: Byte 7 6 5 4 3 2 1 0 Base +14 DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0 Base +15 DO15 DO14 DO13 DO12 DO11 DO10 DO9 DO8 Base +16 DO23 DO22 DO21 DO20 DO19 DO18 DO17 DO16 Base +17 DO31 DO30 DO29 DO28 DO27 DO26 DO25 DO24 The digital output status can be read back through the same location (BASE + 14) 3.
I_REQ: Input REQ Strobe Enabled 1: Use I_REQ edge to latch input data 0: I_REQ is disabled I_TIME0: Input Timer 0 Enable 1: Input is sampled by falling edge of Counter 0 output (COUT0) 0: Input Timer 0 is disabled I_FIFO: Input FIFO Enable Mode 1: Input FIFO is enabled (input data is saved to input FIFO) 0: Input FIFO is disabled TRGPOL: Input Trigger Polarity 1: I_TRG is Rising Edge Active 0: I_TRG is Falling Edge Active I_TRG: External Trigger Enable 1: Wait until I_TRG signal is active, digital input sam
put FIFO to DO registers when output of Counter1 goes low 0: Output Counter 1 is disabled O_FIFO: Output FIFO Enable 1: Output FIFO is enabled (output data is moved from output FIFO) 0: Output FIFO is disabled O_TRG: Digital Output Trigger Signal This bit is used to control the O_TRG output of PCI-7200; the signal is on CN1 pin 36 of PCI-7200, CN1 pin 26 of cPCI7200, CN2 pin 34 of LPCI 7200S when 1: O_TRG 1 goes High (1) 0: O_TRG 1 goes Low (0) X Digital I/O FIFO Status: I_OVR: Input data overrun 1: Digit
3.5 Interrupt Status & Control Register (BASE + 1C) The interrupt mode/status is set/checked through this register.
The following bits are used to check interrupt status: SO_ACK: Status of O_ACK interrupt 1: O_ACK Interrupt occurred 0: No O_ACK interrupt SI_REQ: Status of I_REQ interrupt 1: I_REQ Interrupt occurred 0: No I_REQ Interrupt SI_T0: Status of timer 0 interrupt 1: OUT0 (output of timer 0) Interrupt occurred 0: No timer 0 Interrupt SI_T1: Status of timer 1 interrupt 1: OUT1 (output of timer 1) Interrupt occurred 0: No timer 1 Interrupt SI_T2: Status of timer 2 interrupt 1: OUT2 (output of timer 2) interrupt occu
clock input. X I_REQ Polarity Selection: When the input sampling is controlled by the I_REQ signal only, the I_REQ can be programmed to be rising edge active or falling edge active. REQ_NEG: I_REQ trigger polarity 1: latch input data on falling edge of I_REQ 0: latch input data on rising edge of I_REQ X FIFO Control and Status (cPCI-7200 only): The cPCI-7200 has an extra 2k samples digital input FIFO.
3.6 8254 Timer Registers (BASE + 0) The 8254 timer/counter IC occupies four I/O address. Users can refer to Tundra's or Intel's data sheet for a full description of the 8254 features. Download the 8254 data sheet from the following web site: http://support.intel.com/support/controllers/peripheral/231164.htm or http://www.tundra.com (for Tundra’s 82C54 datasheet).
4 Operation Theory In PCI-7200, there are four data transfer modes can be used for digital I/O access and control, these modes are: 1. Direct Program Control: the digital inputs and outputs can be read/written and controlled by its corresponding I/ O port address directly. 2. Internal Timer Pacer Mode: the digital input and output operations are paced by an internal timer pacer and are transferred by bus mastering DMA. 3.
4.2 Timer Pacer Mode The digital I/O access control is clocked by timer pacer, which is generated by an interval programming timer/counter chip (8254). There are three timers on the 8254. Timer 0 is used to generate timer pacer for digital input and timer 1 is used for digital output. The configuration is illustrated as below.
4.3 External Clock Mode The digital input is clocked by external strobe, which is from Pin 19 (I_REQ) of CN2 (PCI-7200), Pin 24 of CN1 (cPCI-7200), or PIN 33 of CN1A (LPCI-7200S). The operation sequence is very similar to the Timer Pacer Trigger. The only difference is the clock source. 1. The external input strobe is generated from outside device, and goes through the Pin 19 (I_REQ) of CN2 to latch the digital input. 2. The digital input data is saved in FIFO after an I/O strobe signal is coming in. 3.
4.4 Handshaking The PCI-7200 also supports a handshaking digital I/O transfer mode. That is, after input data is ready, an I_REQ is sent from an external device, and I_ACK will go high to acknowledge the data already accessed. I_REQ & I_ACK for Digital Input 1. Digital Input Data is ready. 2. An I_REQ signal is generated for digital input operation. 3. Digital input data is saved to FIFO. 4. An I_ACK signal is generated and sent to an outside device. 5.
O_REQ & O_ACK for Digital Output 1. Digital Output Data is moved from PC memory to FIFO of PCI-7200 by using DMA data mastering data transfer. 2. Move output data from FIFO to digital output circuit. 3. Output data is ready. 4. An O_REQ signal is generated and sent to outside device. 5. After an O_ACK is captured, steps 2-5 will be repeated. ** If the FIFO is not full, the output data is moved form PC‘s main memory to FIFO automatically.
4.5 Timing Characteristic 1. I_REQ as input data strobe (Rising Edge Active) th tl IN_ I_REQ tcyc valid data D10~DI31 valid data ts tn th ≥ 60ns tI ≥ 60ns tCYC ≥ 5 PCI CLK Cycle ts ≥ 2ns tn ≥ 30ns 2.
3. I_REQ & I_ACK Handshaking t5 IN I_REQ t3 t4 IN I_ACK valid data D10~DI31 t1 t1 ≥ 0ns valid data t2 t5 ≥ 60ns t3 ≥ 2 PCI CLK Cycle t2 ≥ 0ns t4 ≥ 1 PCI CLK Cycle Note: I_REQ must be asserted until I_ACK asserts, I_ACK will be asserted until I_REQ de-asserts. 4. O_REQ as output data strobe ts ≥ 19ns th ≥ 2 PCI CLK Cycles Tcyc ≥ 500ns 5.
40 Operation Theory
5 C/C++ Libraries This chapter describes the software library for operating the card. Only the functions in DOS library and Windows 95 DLL are described. Please refer to the PCIS-DASK function reference manual, included on the ADLINK CD, for descriptions of the Windows 98/NT/2000 DLL functions. The function prototypes and some useful constants are defined in the header files LIB directory (DOS) and INCLUDE directory (Windows 95). For the Windows 95 DLL, the developing environment can be Visual Basic 4.
5.1 Libraries Installation Please refer to the “Software Installation Guide” for the detailed information about how to install the software libraries for DOS, or Windows 95 DLL, or PCIS-DASK for Windows 98/NT/2000. Device drivers and DLL functions of Windows 98/NT/2000 are included in the PCIS-DASK. Please refer to the PCIS-DASK user’s guide and function reference, which included on the ADLINK CD, for detailed programming information.
5.2 Programming Guide Naming Convention The functions of the NuDAQ PCI cards or NuIPC CompactPCI cards’ software drivers use full-names to represent the functions' real meaning. The naming convention rules are: In DOS: _{hardware_model}_{action_name}. e.g. _7200_Initial(). All functions in the PCI-7200 driver are named with 7200 as {hardware_model}. But they can be used by PCI-7200, cPCI-7200 and LPCI-7200S.
5.3 _7200_Initial @ Description A PCI-7200 card is initialized according to the card number. Because the PCI-7200 is PCI bus architecture and meets the Plug and Play design, the IRQ and base_address (pass-through address) are assigned by system BIOS directly. Every PCI-7200 card has to be initialized by this function before calling other functions.
ERR_PCIBiosNotExist ERR_PCICardNotExist ERR_PCIIrqNotExist ERR_BaseAddressError C/C++ Libraries 45
5.4 _7200_Switch_Card_No @ Description After initializing more than one PCI-7200 card, this function is used to select which card is currently used.
5.5 _7200_AUX_DI @ Description Read data from auxiliary digital input port of cPCI-7200 card. All four bits input data can be found by using this function. @ Syntax Visual C++ (Windows 95) int W_7200_AUX_DI (U32 *aux_di) Visual Basic (Windows 95) W_7200_DI (aux_di As Long) As Long C/C++ (DOS) int _7200_DI (U32 *aux_di) @ Argument aux_di: returns 4-bit value from auxiliary digital input port.
5.6 _7200_AUX_DI_Channel @ Description Read data from the auxiliary digital input channel of cPCI-7200 card. There are four digital input channels on the cPCI-7200 auxiliary digital input port. When performing this function, the auxiliary digital input port is read and the value of the corresponding channel is returned. * channel means each bit of digital input port.
5.7 _7200_AUX_DO @ Description Write data to auxiliary digital output port. There are four auxiliary digital outputs on the cPCI-7200. @ Syntax Visual C++ (Windows 95) int W_7200_AUX_DO (U32 aux_do) Visual Basic (Windows 95) W_7200_AUX_DO (ByVal aux_do As Long) As Long C/C++ (DOS) int _7200_AUX_DO (U32 aux_do) @ Argument aux_do: value will be written to auxiliary digital output port.
5.8 _7200_AUX_DO_Channel @ Description Write data to auxiliary digital output channel (bit). There are four auxiliary digital output channels on the cPCI-7200. When performing this function, the digital output data is written to the corresponding channel.
5.9 _7200_DI @ Description This function is used to read data from digital input port. There are 32-bit digital inputs on the PCI-7200. Use this function to get all 32 inputs data from _7200_DI. @ Syntax Visual C++ (Windows 95) int W_7200_DI (U32 *di_data) Visual Basic (Windows 95) W_7200_DI (di_data As Long) As Long C/C++ (DOS) int _7200_DI (U32 *di_data) @ Argument di_data: returns all 32-bit value from digital port.
5.10 _7200_DI_Channel @ Description This function is used to read data from digital input channels (bit). There are 32 digital input channels on the PCI-7200. When this function is performed, the digital input port is read and the value of the corresponding channel is returned. * channel means each bit of digital input port.
5.11 _7200_DO @ Description This function is used to write data to the digital output port. There are 32 digital outputs on the PCI-7200.
5.12 _7200_DO_Channel @ Description This function is used to write data to digital output channels (bit). There are 32 digital output channels on the PCI-7200. When performing this function, the digital output data is written to the corresponding channel.
5.13 _7200_Alloc_DMA_Mem @ Description Contact the Windows 95/98 system to allocate a block of contiguous memory for single-buffered DMA transfer. This function is only available in Windows 95/98.
@ Return Code ERR_NoError ERR_SmallerDMAMemAllocated 56 C/C++ Libraries
5.14 _7200_Free_DMA_Mem @ Description Releases system DMA memory. This function is only available in Windows 95/98. @ Syntax Visual C++ (Windows 95) int W_7200_Free_DMA_Mem (U32 handle) Visual Basic (Windows 95) W_7200_Free_DMA_Mem (ByVal handle As Long ) As Long @ Argument handle: The handle of system DMA memory to release.
5.15 _7200_Alloc_DBDMA_Mem @ Description Contact Windows 95/98 system to allocate a block of contiguous memory as circular buffer for double-buffered DMA DI transfer. This function is only available in Windows 95/98 version. For double-buffered transfering, please refer to Section 6 “Double Buffered Mode Principle”.
5.16 _7200_Free_DBDMA_Mem @ Description Releases a system’s circular buffer DMA memory. This function is only available in Windows 95/98. For double-buffered transfer principle, please refer to Section 6 “Double Buffered Mode Principle”. @ Syntax Visual C++ (Windows 95) int W_7200_Free_DBDMA_Mem (U32 handle) Visual Basic (Windows 95) W_7200_Free_DBDMA_Mem (ByVal handle As Long ) As Long @ Argument handle: The handle of system DMA memory to release.
5.17 _7200_DI_DMA_Start @ Description The function will perform digital input N times with DMA data transfer by using one of the following four sampling modes: 1. pacer trigger (internal timer trigger) 2. external rising edge I_REQ 3. external falling edge I_REQ 4. I_REQ & I_ACK handshaking It will take place in the background which will not stop until the Nth input data is transferred or your program execute _7200_DI_DMA_Stop function to stop the process.
bus master operation and can be a large number up to 64 million (2^26) bytes. Since PCI-7200 transfers are always long words, this equals to 16 million long words (2^24). 3. After the input sampling is started, the input data is stored in the FIFO of PCI controller.
Visual Basic (Windows 95) W_7200_DI_DMA_Start (ByVal mode As Byte, ByVal count As Long, ByVal handle As Long, ByVal wait_trg as Byte, ByVal trg_pol As Byte, ByVal clear_fifo As Byte, ByVal disable_di As Byte) As Long C/C++ (DOS) int _7200_DI_DMA_Start (U8 mode, U32 count, U32 *di_buffer, Boolean wait_trig, U8 trig_pol, Boolean clear_fifo, Boolean disable_di) @ Argument mode:Digital Input trigger modes DI_MODE0: Internal timer pacer (TIME 0) DI_MODE1: External signal I_REQ rising edge DI_MODE2: External
DI_WAITING: the input samples waiting rising or falling edge trigger to start DI trig_pol: trigger polarity DI_RISING: rising edge trigger DI_FALLING: falling edge trigger clear_fifo: 0: retain the FIFO data 1: clear FIFO data before perform digital input disable_di: 0: digital input operation still active after DMA transfer complete 1: disable digital input operation immediately when DMA transfer complete @ Return Code ERR_NoError ERR_BoardNoInit ERR_InvalidDIOMode ERR_InvalidDIOCnt ERR_NotDWordAlign ERR
5.18 _7200_DI_DMA_Status @ Description Since the _7200_DI_DMA_Start function is executed in background, users can issue this function to check its operation status. This function only works when double-buffer mode is set as disable.
5.19 _7200_DI_DMA_Stop @ Description This function is used to stop the DMA data transferring. After executing this function, the _7200_DI_DMA_Start function is stopped. The function returns the number of the data which has been transferred, regardless if the digital input DMA data transfer is stopped by this function or by the DMA terminal count, ISR.
5.20 _7200_DblBufferMode @ Description This function is used to enable or disable double buffer mode for DMA DI operation.
5.21 _7200_CheckHalfReady @ Description When you use _7200_DI_DMA_Start to sample digital input data and double buffer mode is set as enable. Users must use _7200_CheckHalfReady to check data ready (data half full) or not in the circular buffer, and using _7200_DblBufferTransfer to get data.
5.22 _7200_DblBufferTransfer @ Description Use this function to copy the input data in the circular buffer to the transfer buffer. It copies half of the circular buffer, either first half or second half, to the transfer buffer.
5.23 _7200_GetOverrunStatus @ Description When using _7200_DI_DMA_Start to convert Digital I/O data with double buffer mode enabled, and not using _7200_DblBufferTransfer to move converted data then double buffer overrun will occur. Use this function to check overrun count.
5.24 _7200_DO_DMA_Start @ Description The function will perform digital output N times with DMA data transfer by using the following four sampling modes: 1. Pacer trigger (internal timer trigger, TIME 1) 2. Internal timer pacer with O_REQ enabled 3. O_REQ & O_ACK handshaking It takes place in the background which will not be stopped until the Nth conversion has been completed or the program executes the _7200_DO_DMA_Stop function to stop the process.
W_7200_Alloc_DMA_Mem must be called to allocate a contiguous DMA memory and get the handle of it. Also W_7200_Alloc_DMA_Mem will attach a buffer to DMA memory. The DO data is stored in the buffer attached to this handle. do_buffer (DOS): the start address of the memory buffer to store the DO data. ** This memory should be double-word alignment repeat: The digital output will be continuous or only one shot. CONTINUOUS: digital output will _7200_DO_DMA_STOP is called.
5.25 _7200_DO_DMA_Status @ Description Since the _7200_DO_DMA_Start function is executed in background, users can issue the function _7200_DO_DMA_Status to check its operation status. @ Syntax Visual C++ (Windows 95) int W_7200_DO_DMA_Status (U8 *status, U32 * count) Visual Basic (Windows 95) W_7200_DO_Status ( status As Byte, count As Long ) As Long C/C++ (DOS) int _7200_DO_DMA_Status (U8 *status , U32 *count) @ Argument status: status of the DMA data transfer.
5.26 _7200_DO_DMA_Stop @ Description This function is used to stop the DMA DO operation. After executing this function, the _7200_DO_DMA_Start function is stopped. The function returns the number of the data which has been transferred, regardless if the digital output DMA data transfer is stopped by this function or by the DMA terminal count ISR.
5.27 _7200_DI_Timer @ Description This function is used to set the internal timer pacer for digital input. There are two configurations for the internal timer pacer: 1. Non-cascaded (One COUNTER 0 only) 8254 Timer/Counter 4MHz Input CLK0 GATE0 Counter 0 OUT0 Digital Input Trigger Timer pacer frequency = 4Mhz / C0 2.
@ Argument c0: frequency divider of Counter #0. Valid value ranges from 2 to 65535. c2: frequency divider of Counter #2. Valid value ranges from 2 to 65535. Note: Since the Integer type in Visual Basic is a signed integer. Its range is within -32768 and 32767. In Visual Basic, to set c0 or c2 to a value larger than 32767, set it as the intended value minus 65536. For example, to set c0 as 40000, set c0 as 40000-65536=-25536.
5.28 _7200_DO_Timer @ Description This function is used to set the internal timer pacer for digital output. There are two configurations for the internal timer pacer: 1. Non-cascaded (One COUNTER 0 only) 8254 Timer/Counter 4MHz Input CLK0 GATE0 Counter 1 OUT0 Digital Output Trigger Timer pacer frequency = 4Mhz / C1 2.
@ Argument c1 : frequency divider of Counter #1 c2 : frequency divider of Counter #2 Note : Since the Integer type in Visual Basic is a signed integer. Its range is within -32768 and 32767. In Visual Basic, to set c1 or c2 to a value larger than 32767, set it as the intended value minus 65536. For example, to set c0 as 40000, set c0 as 40000-65536=-25536.
78 C/C++ Libraries
6 Double Buffer Mode Principle The data buffer for a double-buffered DMA DI operation is logically a circular buffer divided into two equal halves. The double buffered DI begins when the device starts writing data into the first half of the circular buffer (Figure 6-1a). After device begins writing to the second half of the circular buffer, users can copy the data from the first half into the transfer buffer (Figure 6-1b).
half-full and ready for copying to the transfer buffer. Then call _7200_DblBufferTransfer() to copy data from the ready half buffer to the transfer buffer. In Windows 95, W_7200_Alloc_DBDMA_Mem() is needed to allocate a contiguous DMA memory for the circular buffer. The buf_size argument of W_7200_Alloc_DBDMA_Mem() is the half size of circular buffer in byte, that is, the size of each half buffer in byte. The DMA memory is referenced by the return parameter handle.
7 Limitations The 12MB/sec data transfer rate can only be possibly achieved in systems where the PCI-7200 card is the only device using the bus, but the speed cannot be guaranteed due to the limited FIFO depth. The PCI-7200 supports three input clock modes, internal clock, external clock, and handshaking modes. The first two modes cannot guarantee the input data integrity in high-speed data rate because of the limited FIFO depth and PCI-bus latency variation.
82 Limitations
Warranty Policy Thank you for choosing ADLINK. To understand your rights and enjoy all the after-sales services we offer, please read the following carefully. 1. Before using ADLINK’s products please read the user manual and follow the instructions exactly. When sending in damaged products for repair, please attach an RMA application form which can be downloaded from: http:// rma.adlinktech.com/policy/. 2.
3. Our repair service is not covered by ADLINK's guarantee in the following situations: X X X X X X X X X Damage caused by not following instructions in the User's Manual. Damage caused by carelessness on the user's part during product transportation. Damage caused by fire, earthquakes, floods, lightening, pollution, other acts of God, and/or incorrect usage of voltage transformers. Damage caused by unsuitable storage environments (i.e. high temperatures, high humidity, or volatile chemicals).
