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Advance Technologies; Automate the World.

Manual Rev.: 2.01

Revision Date: November 13, 2014

Part No: 50-15086-1010

cPCI-6520

6U CompactPCI® 3rd Generation

Intel® Core™ i7 Processor Blade

User’s Manual

Summary of content (130 pages)

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cPCI-6520 6U CompactPCI® 3rd Generation Intel® Core™ i7 Processor Blade User’s Manual Manual Rev.: 2.01 Revision Date: November 13, 2014 Part No: 50-15086-1010 Advance Technologies; Automate the World.
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Revision History Revision Release Date Description of Change(s) 2.00 2013/03/13 Initial release 2.
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cPCI-6520 Preface Copyright 2013 ADLINK Technology Inc. This document contains proprietary information protected by copyright. All rights are reserved. No part of this manual may be reproduced by any mechanical, electronic, or other means in any form without prior written permission of the manufacturer.
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Using this Manual Audience and Scope The cPCI-6520 User’s Manual is intended for hardware technicians and systems operators with knowledge of installing, configuring and operating industrial grade computer systems. Manual Organization This manual is organized as follows: Chapter 1, Introduction: Introduces the cPCI-6520, its features, block diagrams, and package contents. Chapter 2, Specifications: Presents detailed specification information.
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cPCI-6520 Conventions Take note of the following conventions used throughout this manual to make sure that users perform certain tasks and instructions properly. Additional information, aids, and tips that help users perform tasks. NOTE: CAUTION: WARNING: Preface Information to prevent minor physical injury, component damage, data loss, and/or program corruption when trying to complete a task.
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cPCI-6520 Table of Contents Revision History...................................................................... ii Preface .................................................................................... iii List of Figures ........................................................................ ix List of Tables.......................................................................... xi 1 Introduction ........................................................................ 1 1.1 Overview.........
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4.2 cPCI-6520 Assembly Layout.............................................. 22 4.3 cPCI-6520 Front Panel ...................................................... 23 4.4 Connector Pin Assignments............................................... 24 4.5 Switches and Buttons ........................................................ 38 5 Getting Started .................................................................. 43 5.1 CPU and Heatsink .............................................................
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cPCI-6520 List of Figures Figure 1-1: Figure 4-1: Figure 4-2: Figure 4-3: cPCI-6520 Functional Block Diagram.............................. 4 cPCI-6520 Board Layout ............................................... 21 cPCI-6520 Assembly Layout ......................................... 22 cPCI-6520 Front Panel ..................................................
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cPCI-6520 List of Tables Table 2-1: cPCI-6520 Blade Specifications ...................................... 9 Table 2-2: cPCI-6520 I/O Connectivity ...........................................
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cPCI-6520 1 Introduction 1.1 Overview The cPCI-6520 is a 6U CompactPCI® processor blade in single-slot (4HP) width form factor featuring a single 22nm FC-BGA 3rd generation Intel® Core™ i7 Processor with quad/dual-cores mated with the Mobile Intel® QM77 Express Chipset. The cPCI-6520 supports dual channel DDR3-1066/1333/1600 ECC SDRAM with one channel in a SO-CDIMM socket and one channel of soldered onboard memory (total memory capacity up to 16GB).
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The cPCI-6520 supports operation in both a system slot and in a peripheral slot as a standalone blade. The cPCI-6520 is compliant with the PICMG 2.9 specification and supports system management functions based on the Intelligent Platform Management Interface (IPMI) as well as hardware monitoring of physical characteristics such as CPU and system temperature, DC voltages and power status.
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cPCI-6520 1.2 Features X 6U CompactPCI® processor blade in 4HP width form factor X Supports FCBGA package 4-core 3rd Generation Intel® Core™ i7-3615QE 2.
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GbE2 USB1 USB2 USB3 DP1 DP2 Front Panel GbE1 COM1 1.3 Block Diagram COM1 Intel 82579LM ECC SO-CDIMM, max. 8GB PCIe x1 Soldered w/ ECC, max. 8GB 3x USB 3.0 7-pin DP-D BIOS PCIe x1 DP-C SPI Intel 82574 SATA2 DDR3 1066/1333 PCIe x4 DMI Intel® Core™ i7 w/ ECC Intel® BD82QM77 PCH FDI PCIe x4 PI7C9X130 PCIe x8 Gen3 PI7C9X130 PCI 64b/133M PMC PCI 64b/66M XMC.3 SIO eDP COM6 TPM BMC KB/MS COM2/3 Rear I/O IPMB 0/1 J1/J2 2x PCIe x1 LPC SATA0 2.5” HDD 1x USB 3.0 5x USB 2.
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cPCI-6520 1.4 Product List Products included in the cPCI-6520 are: Processor Blade X cPCI-6520: 4HP width (single-slot) 6U CompactPCI blade featuring single FCBGA package 3rd Generation Intel® Core™ i7 processor with quad/dual cores, two channel DDR3-1066/1333/1600 ECC SDRAM, 2x GbE, 2x DisplayPorts, 3x USB 3.0, 1x RS-232/422/485 serial port in RJ-45 connector, SATA direct connector for onboard 2.5" drive, onboard CompactFlash socket, PMC/XMC site, optional CFast support by adapter board.
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1.5 Package Contents The cPCI-6520 is packaged with the following components. If any of the items on the contents list are missing or damaged, retain the shipping carton and packing material and contact the dealer for inspection. Please obtain authorization before returning any product to ADLINK. The packing contents of the cPCI-6520 are non-standard configurations and may vary depending on customer requests.
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cPCI-6520 The contents of non-standard cPCI-6520 configurations may vary depending on the customer requirements. NOTE: CAUTION: Introduction This product must be protected from static discharge and physical shock. Never remove any of the components except at a static-free workstation. Use the anti-static bag shipped with the product when putting the board on a surface.
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cPCI-6520 2 Specifications 2.1 cPCI-6520 Blade Specifications CompactPCI® Standards • • • • PICMG® 2.0 CompactPCI® Rev. 3.0 PICMG® 2.1 Hot Swap Specification Rev.2.0 PICMG® 2.9 System Management Bus Rev. 1.0 PCIMG® 2.16 Packet Switching Backplane Rev.1.0 Mechanical • • • • Standard 6U CompactPCI® Board size: 233.35mm x 160mm Single-slot width (4HP, 20.32mm) CompactPCI® connectors with J1, J2, J3, J4 and J5 Processor 22nm FCBGA Intel® Core™ i7 Processor • 4-core Intel® Core i7-3615QE Processor, 2.
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Gigabit Ethernet • One front panel GbE LAN port from Intel® 82579LM PHY controller and one front panel GbE LAN from Intel 82574 Gigabit Ethernet controller • Two 10/100/1000BASE-T ports routed to J3 for PICMG 2.16 • Two additional 10/100/1000BASE-T ports from Intel® 82576EB Gigabit Ethernet controllers on RTM (cPCIR6100 or cPCI-R6110) Serial Ports Up to three 16C550 serial ports • One DB-9 RS-232/422/485 serial port on front panel • Two serial ports routed to rear I/O through J3 USB 2.0 • Six USB 2.
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cPCI-6520 Environmental • Operating Temperature2: Standard: 0 to 60°C with forced air flow ETT: -20°C to 70°C with forced air flow (cPCI-ET6520) EX: -40°C to 85°C with forced air flow (Core™ i7-3555LE & Core™ i7-3517UE only) • Storage Temperature: -40°C to 85°C • Humidity: 95% non-condensing • Shock: 15G peak-to-peak, 11ms duration, non-operating • Vibration3: Operating 2 Grms, 5-500Hz, each axis w/o hard drive EMI • CE EN55022 • FCC Class A Table 2-1: cPCI-6520 Blade Specifications Notes: 1.
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2.2 I/O Connectivity RTM1 cPCI-6520 Faceplate Onboard J3/4/5 GbE Y x2 — Y x2 COM Y x1 — Y x2 USB 2.0 — — Y x6 USB 3.0 Y x3 — Y x1 DisplayPort Y x2 — eDP — Y x1 DVI — — Y x1 VGA — — Y x1 PMC — Y x1 — Y x1 — XMC SATA — Y x22 Y x3 Y x12 CFast CF — Y — PS/2 KB/MS — — Y x1 HDA — — Y Status LEDs Y x4 — — General Purpose LEDs Y x8 — — Load BIOS Default Button — Y — Reset Button Y — — Table 2-2: cPCI-6520 I/O Connectivity Notes: 1.
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cPCI-6520 2.3 Power Requirements In order to guarantee a stable functionality of the system, it is recommended to provide more power than the system requires. An industrial power supply unit should be able to provide at least twice as much power as the entire system requires of each voltage. An ATX power supply unit should be able to provide at least three times as much power as the entire system requires of each voltage.
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Power Consumption This section provides information on the power consumption of the cPCI-6520 when using Intel® Core™ i7 processors with 4GB DDR31333 soldered memory and onboard ADLINK ASD25 64GB SATA SSD. Power consumption at 100% CPU usage was measured by running Intel Thermal Analysis Tool 4.3. Quad-Core Intel® Core™ i7-3615QE, 2.3GHz, TDP 45W OS / Mode 5V Current (A) 3.3V Current (A) 12V Current (A) Total Power (W) DOS / idle 4.48 2.80 0.19 33.9 Win7 / idle 3.34 2.62 0.20 27.
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cPCI-6520 3 Functional Description The following sections describe the cPCI-6520 features and functions. 3.1 Processors The 3rd Generation Intel® Core™ i7 Processor is the next generation of 64-bit, multi-core mobile processors built on 22-nanometer process technology. Based on a new micro-architecture, the processor is designed for a two-chip platform. The two-chip platform consists of a processor and Platform Controller Hub (PCH).
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Supported Technologies X Intel® Virtualization Technology for Directed I/O (Intel® VT-d) X Intel® Virtualization Technology (Intel® VT-x) X Intel® vPro Technology (Intel® VT) X Intel® Trusted Execution Technology (Intel® TXT) X Intel® Hyper-Threading Technology X Intel® 64 Architecture X Intel® Turbo Boost Technology 2.
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cPCI-6520 3.2 Chipset The cPCI-6520 incorporates the Intel® QM77 Platform Controller Hub (PCH). Intel® QM77 Platform Controller Hub X PCI Express Base Specification, Revision 2.0 support for up to eight ports with transfer rate up to 5 GT/s X Supports dual display X ACPI Power Management Logic Support, Revision 4.0a X Enhanced DMA controller, interrupt controller, and timer functions X Integrated Serial ATA host controllers with independent DMA operation on up to six ports and SATA 6.
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3.3 PMC/XMC Site The cPCI-6520 supports one PMC or XMC site for front panel I/O expansion. The PMC site provides a maximum 32/64-bit, 33/66/133MHz PCI bus link using a Pericom PI7C9X130 PCIe-to-PCI-X bridge and PCIe x4 link. The PMC site supports +3.3V and 5V signaling. The XMC site provides a PCIe x8 lane. 3.
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cPCI-6520 3.6 Intel® Active Management Technology Intel® Active Management Technology (Intel® AMT) is a hardware based technology for remotely managing and securing PCs out-of-band. Intel® AMT includes hardware-based remote management, security, power-management, and remote-configuration features. Intel® AMT allows remote access to a system when traditional techniques and methods are not available. 3.
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cPCI-6520 4 Board Interfaces 4.1 cPCI-6520 Board Layout SW13 CN10 CN13 BT2 J5 CN3 CN14 SW7 SW_COMPW1 CN5 CN9 SW1 J4 SW12 SW_VIO1 SW_MOD1 SW_IPMCDEG1 SW_COMDEG1 CN2 J N2 J N1 CN1 J3 Onboard Memory JN4 JN3 J2 CN6 CN7 CN8 SW_PMC1 DP1 J1 DP2 BT2 Battery JN1/2/3/4 PMC connectors CN1 SODIMM Socket SW1 BIOS default button CN2 XMC connector SW12 COM RS-232/422/485 CN5 COM1 port SW13 Reserved CN6/7/8 USB 3.
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4.2 cPCI-6520 Assembly Layout DB-LSATA Onboard 2.
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cPCI-6520 4.3 cPCI-6520 Front Panel GbE 1/2 PMC/XMC COM1 USB 3.0 General Purpose LEDs DisplayPort Reset Button Status LEDs Figure 4-3: cPCI-6520 Front Panel Status LEDs LED Color Power Green Condition OFF System is off ON System is on Blink Fail to power on (payload power failure) OFF Handles closed, System is on Fast Blink Preparing to shut down system (LED: 0.1s on, 0.9s off.) ON Handles open and blade ready to be removed Slow Blink Voltages out of tolerance: 3.3V, 5V, 12V, 1.
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4.4 Connector Pin Assignments See “cPCI-6520 Board Layout” on page 21 for connector locations.
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cPCI-6520 COM1 (RJ-45) Pin # RS-232 RS-422 RS-485 1 DCD# TX- Data- 2 RTS# — — 3 DSR# — — 4 TXD RX+ — 5 RXD TX+ Data+ 6 GND — — 7 CTS# — — 8 DTR#L RX- — 8 1 COM1 RJ-45 to DB-9 Cable Pin # RS-232 RS-422 RS-485 1 DCD# TX- Data- 2 RXD TX+ Data+ 3 TXD RX+ — 4 DTR#L RX- — 5 GND — — 6 DSR# — — 7 RTS# — — 8 CTS# — — 9 — — — Board Interfaces 6 1 5 25
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USB 3.
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cPCI-6520 Onboard Connectors SATA Connector (CN10) Pin # Signal 1 2 3 4 5 6 7 GND TXP TXN GND RXN RXP GND 1 7 SATA Connector on DB-LSATA Pin # Signal S1 GND S2 TX+ S3 TX- S4 GND S5 RX- S6 RX+ S7 GND P1 NC P2 NC P3 NC P4 GND P5 GND P6 GND P7 5V P8 5V P9 5V P10 GND P11 Reserved P12 GND P13~P15 12V Board Interfaces S1 Signal S7 P1 Power P15 27
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CFast Socket (on DB-CFast) Pin # 28 Signal Name Ground S1 SATA_TX-P S2 SATA_TX-N S3 Ground S4 SATA_RX-N S5 SATA_RX-P S6 Ground S7 CFast_CDI P1 Ground P2 NC P3 NC P4 NC P5 NC P6 Ground P7 CFast_LED1 P8 CFast_LED2 P9 NC P10 NC P11 NC P12 P3V3 P13 P3V3 P14 Ground P15 Ground P16 CFast_CDO P17 1 24 P1 S1 Board Interfaces
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cPCI-6520 DB-LSATA Connector (CN9) Signal Name Pin # Pin # Signal Name GND 1 2 GND GND 3 4 GND GND 5 6 GND GND 7 8 GND GND 9 10 GND GND 11 12 GND GND 13 14 GND GND 15 16 GND GND 17 18 GND GND 19 20 GND GND 21 22 GND GND 23 24 GND GND 25 26 GND GND 27 28 GND GND 29 30 GND P3V3 31 32 P5V P3V3 33 34 P5V P3V3 35 36 P5V P3V3 37 38 P5V NC 39 40 P12V CFAST_CDI 41 42 P12V CFAST_CDO 43 44 P12V GND 45 46 GND GND 47 48
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PMC Connector (JN1, JN2, JN3, JN4) Pin# JN1 Signal JN2 Signal JN3 Signal JN4 Signal 1 PMC_TCK P12V NC PIO1 2 N12V* PMC_TRST-L GND PIO2 3 GND PMC_TMS GND PIO3 4 PCIX_INTA-L NC (PMC_TDO) PCIX_CBE-L7 PIO4 5 PCIX_INTB-L PMC_TDI PCIX_CBE-L6 PIO5 6 PCIX_INTC-L GND PCIX_CBE-L5 PIO6 7 PMC_MOD-L1 GND PCIX_CBE-L4 PIO7 8 P5V NC GND PIO8 9 PCIX_INTD-L NC PMC_VIO PIO9 10 NC NC PCIX_PAR64 PIO10 11 GND PMC_MOD-L2 PCIX_AD63 PIO11 12 P3V3_PMCAUX P3V3 PCIX_AD62
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cPCI-6520 Pin# JN1 Signal JN2 Signal JN3 Signal JN4 Signal 33 PCIX_FRAME-L GND GND PIO33 34 GND NC PCIX_AD48 PIO34 35 GND PCIX_TRDY-L PCIX_AD47 PIO35 36 PCIX_IRDY-L P3V3 PCIX_AD46 PIO36 37 PCIX_DEVSEL-L GND PCIX_AD45 PIO37 38 P5V PCIX_STOP-L GND PIO38 39 PCIX_PCIXCAP PCIX_PERR-L GND PIO39 40 PCIX_LOCK-L GND PCIX_AD44 PIO40 41 NC P3V3 PCIX_AD43 PIO41 42 NC PCIX_SERR-L PCIX_AD42 PIO42 43 PCIX_PAR PCIX_CBE-L1 PCIX_AD41 PIO43 44 GND GND GND PIO44
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XMC Connector (CN2) F1 F19 A1 A19 Pin# A B C D E F 1 RXP RXN 3.3V NC NC VPWR 2 GND GND Not used GND GND PCIE_RST-L 3 NC NC 3.3V NC NC VPWR 4 GND GND Not used GND GND Not used 5 NC NC 3.3V NC NC VPWR 6 GND GND Not used GND GND +12V 7 NC NC 3.
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cPCI-6520 CompactPCI J1 Connector Pin Assignment Pin Z A B C D E F 25 GND +5V REQ64# ENUM# +3.
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CompactPCI J2 Connector Pin Assignment Pin Z A B C D E F 22 GND GA4 GA3 GA2 GA1 GA0 GND 21 GND CLK6 GND NC NC NC GND 20 GND CLK5 GND NC GND NC GND 19 GND GND GND NC NC NC GND 18 GND NC NC NC GND NC GND 17 GND NC GND RSTBTN# REQ6# GNT6# GND 16 GND NC NC DEG# GND NC GND 15 GND NC GND FAL# REQ5# GNT5# GND 14 GND AD35 AD34 AD33 GND AD32 GND 13 GND AD38 GND V(I/O) AD37 AD36 GND 12 GND AD42 AD41 AD40 GND AD39 GND 11 G
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cPCI-6520 CompactPCI J3 Pin Assignment Pin Z A B C D E F P5V P5V P12V P5V P5V GND 18 GND LAN3_TXD1+ LAN3_TXD0- GND LAN3_TXD2+ LAN3_TXD2- GND 17 GND LAN3_TXD1+ LAN3_TXD1- GND LAN3_TXD3+ LAN3_TXD3- GND 16 GND LAN4_TXD0+ LAN4_TXD0- GND LAN4_TXD2+ LAN4_TXD2- GND 15 GND LAN4_TXD1+ LAN4_TXD1- GND LAN4_TXD3+ LAN4_TXD3- GND 19 GND 14 GND USB-OC5# USB-OC6# USB-OC7# USB-OC8# USB-OC9# GND 13 GND USB-P8+ USB-P8- GND USB-P9+ USB-P9- GND 12 GND USB-P6+ USB-P6- GND
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CompactPCI J4 Connector Pin Assignment Pin Z A B C D E F 25 GND PMC IO:P1 PMC IO:N1 NC PMC IO:P2 PMC IO:N2 GND 24 GND PMC IO:P3 PMC IO:N3 NC PMC IO:P4 PMC IO:N4 GND 23 GND NC NC NC NC NC GND 22 GND PMC IO:P5 PMC IO:N5 NC PMC IO:P6 PMC IO:N6 GND 21 GND PMC IO:P7 PMC IO:N7 NC PMC IO:P8 PMC IO:N8 GND 20 GND NC NC NC NC NC GND 19 GND PMC IO:17 PMC IO:19 NC PMC IO:18 PMC IO:20 GND 18 GND PMC IO:21 PMC IO:23 NC PMC IO:22 PMC IO:24 GND 17 GND
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cPCI-6520 CompactPCI J5 Pin Assignment Pin Z A B C D 22 GND Power LED 21 GND eDP_TX1+ eDP_TX1- 20 GND eDP_TX0+ eDP_TX0- GND 19 GND GND GND GND 18 GND NC NC GND NC E F LAN2_LINK_ACT# LAN2_VCC_TERM LAN3_LINK_ACT# LAN3_VCC_TERM GND GND eDP_TX3+ eDP_TX3- GND eDP_TX2+ eDP_TX2- GND eDP_AUX+ eDP_AUX- GND NC GND 17 GND NC NC GND NC NC GND 16 GND GND GND eDP_HPD# GND GND GND 15 GND NC NC GND SATA-RX5+ SATA-RX5- GND 14 GND NC NC GND SATA-TX5+ SATA-TX5-
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4.5 Switches and Buttons See “cPCI-6520 Front Panel” on page 23 and “cPCI-6520 Board Layout” on page 21 for switch locations. System Reset Button The cPCI-6520 has a system reset button on the front panel. See “cPCI-6520 Front Panel” on page 23 for the button location. Load BIOS Default Button (SW1) Press switch SW1 to load the default BIOS settings. COM1 Mode Switch (SW12) Switch SW12 sets the mode of the COM1 port on the front panel.
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cPCI-6520 IPMC Mode Switch (SW_MOD1) Switch SW_MOD1 is a multi purpose switch that allows users to define the blade operating mode. All are set to OFF by default. ON 1 Pin# Status 1 4 3 4 Description OFF Reserved OFF When the system does not include a Chassis Management Module (CMM), set this pin to OFF to allow IPMI to run in "without CMM mode" (default). ON When the system includes a CMM, set this pin to ON to allow IPMI to run in "with CMM mode".
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PMC Frequency Switch (SW_PMC1) Switch SW_PMC1 sets the frequency and mode of the PMC slot. All are set to OFF by default.. ON 1 Pin# 1 2 3 4 2 3 Status 4 Function OFF 64-bit bus (default) ON 32-bit bus OFF PCI 33 MHz (default). ON PCI 66 MHz OFF PCI-X mode (default) PCI mode OFF PCI-X 133 MHz (default) ON PCI-X 100M Hz PMC VIO Function (SW_VIO1) Switch SW_VIO1 sets the VIO signal voltage of the PMC slot. 1 ON Status 40 OFF Function OFF (short 1-2) 5V ON (short 2-3) 3.
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cPCI-6520 SW_IPMCDEG1 Switch SW_IPMCDEG1 is for debugging purposes and should be left in the default setting of “All OFF”. 1 ON 2 NOTE: Pin Function 1, 4 ON Force power on 2, 3 ON Disable IPMC latch All ON Disable IPMC All OFF IPMC enable (Default) When the cPCI-6520 is mated with the cPCI-R6700, it is necessary to set pins 1, 4 on the SW_IPMCDEG1 to ON (Force power on).
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cPCI-6520 5 Getting Started This chapter describes the installation of the following components to the cPCI-6520 and rear transition modules: X CompactFlash card X 2.5” SATA hard drive X CFast card X PMC/XMC module installation 5.1 CPU and Heatsink The cPCI-6520 comes with CPU(s) and heatsink pre-installed. Removal of heatsink/CPU by users is not recommended. Please contact your ADLINK service representative for assistance. 5.
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Installing a CF card 1. A CompactFlash can be installed in the location marked below. 2. Turn the blade over (solder side up). Unscrew the two screws securing the CompactFlash retention bracket as indicated below and remove the CompactFlash retention holder.
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cPCI-6520 3. Turn the blade over (component side up), then align and insert the CompactFlash card into the slot until it is properly seated. 4. 4.Align the retention bracket to the screw holes. Turn the blade over (solder side up) and secure CompactFlash card retention bracket to the blade with two screws indicated as below.
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5. The CompactFlash card installation is completed. Removing a CF card with SATA Drive installed To remove a CompactFlash card, reverse the above steps. If CompactFlash card removal is required when a SATA drive is installed, follow the instructions below. 1. Remove the CompactFlash bracket without removing the drive bracket by first turning over the cPCI-6520 blade and unscrewing the CompactFlash bracket as shown below.
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cPCI-6520 2. Remove the screw securing the CompactFlash bracket to the drive assembly as marked below. 3. Remove the CompactFlash card.
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5.3 SATA Drive Installation The cPCI-6520 provides space to install a slim type 2.5” SATA drive. Installing a SATA Drive - cPCI-6520 1. Locate the LB-LSATA daughter board in the package and connect it to slim type 2.5"drive. 2. Find the drive bracket in the package and orient the drive and bracket as shown below.
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cPCI-6520 3. Secure the drive to the bracket by fastening the four screws provided in the package in the locations marked below. 4. Align and assemble the connector on the DB-LSATA to onboard SATA connector (CN9) by fastening two screws marked as below.
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5. Secure the drive bracket by securing a screw at the CF bracket through to the drive bracket shown as below. 6. Turn the blade over and secure two screws marked as below.
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cPCI-6520 5.4 PMC/XMC Installation The cPCI-6520 series provides space to install a PMC or XMC module. 1. A PMC/XMC mezzanine card can be installed on the cPCI-6520 in the location indicated below. 2. Remove the PMC filler plate on the front panel.
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3. Align the connectors on the PMC/XMC module to the PMC/XMC connectors on cPCI-6520 blade. Press down to secure the PMC/XMC module to the cPCI-6520. 4. Remove the black plastic caps securing the mounting screws to the front panel.
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cPCI-6520 5.5 CFast Card installation The cPCI-6520 Series provides space to install a CFast card (optional accessory P/N: 91-37572-000E; please contact your ADLINK representative for availability). The CFast card space is shared with the 2.5" SATA drive and both cannot be installed simultaneously. 1. Prepare a CFast adapter board. 2. Align and insert the CFast card into the CFast adapter board.
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3. 3.The CFast adapter with card can be installed at the SATA connector location as indicated below. 4. 4.Flip the CFast adapter so that the card is face down. Align and connect the CFast adapter to the onboard SATA connector until it is properly seated.
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cPCI-6520 5. 5.Secure the CFast adapter with two screws as shown below.
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cPCI-6520 6 Driver Installation The cPCI-6520 drivers are available from the ADLINK All-In-One DVD at X:\cPCI\cPCI-6520\, or from the ADLINK website (http://www.adlinktech.com). ADLINK provides validated drivers for Windows XP Professional and Windows 7. We recommend using these drivers to ensure compatibility. The VxWorks BSP can also be downloaded from the cPCI-6520 product page on the ADLINK website. 1. Install the Windows operating system before installing any driver.
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9. Install the TPM utilities by extracting and running the program in …\TPM\ Atmel_TPM_Dvr_WinXP_32_64 _4-0-0-msi.zip. 10.Install the audio drivers and utility by extracting and running the program in …\Audio\Realtek_High_Definition _Audio_Win7_32_6-0-1-6602.zip. 11. Install the Intel Management Engine Interface driver for iAMT support by extracting and running the program in ...\Chipset\ Intel_Management_Engine_Interface _AllOS__8-0-10-1464.zip.
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cPCI-6520 7 Utilities 7.1 Watchdog Timer This section describes the operation of the cPCI-6520’s watchdog timer (WDT). The primary function of the WDT is to monitor the cPCI-6520's operation and to reset the system if a software application fails to function as programmed.
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Sample Code The sample program written in C shown below offers an interactive way to test the Watchdog Timer under DOS. #include #include
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cPCI-6520 tempCount = count_value / 60; if((count_value%60) > 30) tempCount++; if(tempCount > 255) tempCount = 255; printf("WDT timeout in %d minutes.
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registerValue |= 0x02; // set GPIO2 is active outportb(W83627UHG_ioPort+1, registerValue); outportb(W83627UHG_ioPort, 0xe4); registerValue = inportb(W83627UHG_ioPort+1); registerValue &= 0xf7; // set GPIO23 is output function outportb(W83627UHG_ioPort+1, registerValue); outportb(W83627UHG_ioPort, 0xe5); registerValue = inportb(W83627UHG_ioPort+1); registerValue &= 0xf7; // set GPIO23 is Low outportb(W83627UHG_ioPort+1, registerValue); } printf("WDT timeout in %d seconds.
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cPCI-6520 registerValue = inportb(W83627UHG_ioPort+1); registerValue |= 0x08; // set GPIO23 is High outportb(W83627UHG_ioPort+1, registerValue); printf("WDT is Disabled.\n"); } outportb(W83627UHG_ioPort, 0x07); outportb(W83627UHG_ioPort+1, 8); // CR07 set Logical Device 8 outportb(W83627UHG_ioPort, 0xf6); outportb(W83627UHG_ioPort+1, tempCount); // set WDT count value..
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cPCI-6520 8 BIOS Setup The following chapter describes basic navigation for the AMIBIOS®8 BIOS setup utility. 8.1 Starting the BIOS To enter the setup screen, follow these steps: 1. Power on the motherboard 2. Press the < Delete > key on your keyboard when you see the following text prompt: < Press DEL to run Setup > 3. After you press the < Delete > key, the main BIOS setup menu displays. You can access the other setup screens from the main BIOS setup menu, such as Chipset and Power menus.
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Setup Menu The main BIOS setup menu is the first screen that you can navigate. Each main BIOS setup menu option is described in this user’s guide. The Main BIOS setup menu screen has two main frames. The left frame displays all the options that can be configured. “Grayed” options cannot be configured, “Blue” options can be. The right frame displays the key legend. Above the key legend is an area reserved for a text message. When an option is selected in the left frame, it is highlighted in white.
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cPCI-6520 There is a hot key legend located in the right frame on most setup screens. NOTE: The < F8 > key on your keyboard is the Fail-Safe key. It is not displayed on the key legend by default. To set the Fail-Safe settings of the BIOS, press the < F8 > key on your keyboard. It is located on the upper row of a standard 101 keyboard. The Fail-Safe settings allow the motherboard to boot up with the least amount of options set. This can lessen the probability of conflicting settings.
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68 F2 The < F2 > key on your keyboard is the previous values key. It is not displayed on the key legend by default. To set the previous values settings of the BIOS, press the < F2 > key on your keyboard. It is located on the upper row of a standard 101 keyboard. The previous values settings allow the motherboard to boot up with the least amount of options set. This can lessen the probability of conflicting settings. F3 The < F3 > key on your keyboard is the optimized defaults key.
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cPCI-6520 Press the < Enter > key to save the configuration and exit. You can also use the < Arrow > key to select Cancel and then press the < Enter > key to abort this function and return to the previous screen. ESC The < Esc > key allows you to discard any changes you have made and exit the Setup. Press the < Esc > key to exit the setup without saving your changes. The following screen will appear: Press the < Enter > key to discard changes and exit.
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8.2 Main Setup When you first enter the Setup Utility, you will enter the Main setup screen. You can always return to the Main setup screen by selecting the Main tab. There are two Main Setup options. They are described in this section. The Main BIOS Setup screen is shown below. System & Board Info The Main BIOS setup screen reports BIOS and Board version information. System Time/System Date Use this option to change the system time and date. Highlight System Time or System Date using the < Arrow > keys.
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cPCI-6520 8.3 Advanced BIOS Setup Select the Advanced tab from the setup screen to enter the Advanced BIOS Setup screen. You can select any of the items in the left frame of the screen, such as SuperIO Configuration, to go to the sub menu for that item. You can display an Advanced BIOS Setup option by highlighting it using the < Arrow > keys. The Advanced BIOS Setup screen is shown below. The sub menus are described on the following pages.
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8.3.1 PCI Subsystem Settings You can use this screen to select options for the PCI Subsystem Settings. Use the up and down < Arrow > keys to select an item. Use the < + > and < - > keys to change the value of the selected option. A description of the selected item appears on the right side of the screen. The settings are described on this page. The screen is shown below.
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cPCI-6520 VGA Palette Snoop Enables or disables VGA Palette Registers Snooping. Set this value to Disabled/Enabled. PERR# Generation Enables or disables PCI Device to Generate PERR#. Set this value to Disabled/Enabled. SERR# Generation Enables or disables PCI Device to Generate SERR#. Set this value to Disabled/Enabled. 8.3.2 ACPI Settings You can use this screen to select options for the ACPI Advanced Configuration Settings. Use the up and down < Arrow > keys to select an item.
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ACPI Sleep State Select the highest ACPI sleep state the system will enter, when the SUSPEND button is pressed. Set this value to S1 only, Suspend Disable.
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cPCI-6520 Security Device Support OS will not show TPM. Reset of platform is required. Set this value to Enabled/Disabled. TPM State Determine whether TPM state change requires Password Authentication. Set this value to Enabled/Disabled. Pending TPM operation Schedule TPM operation. The settings for this value are Enable, Disable and Clear.
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8.3.4 CPU Configuration You can use this screen to select options for the CPU Configuration Settings. Use the up and down < Arrow > keys to select an item. Use the < + > and < - > keys to change the value of the selected option. A description of the selected item appears on the right side of the screen. The settings are described on the following pages. An example of the CPU Configuration screen is shown below.
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cPCI-6520 Limit CPUID Maximum When the computer is booted up, the operating system executes the CPUID instruction to identify the processor and its capabilities. Before it can do so, it must first query the processor to find out the highest input value CPUID recognized. This determines the kind of basic information CPUID can provide the operating system. This option allows you to circumvent problems with older operating systems.
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8.3.5 SATA Configuration You can use this screen to select options for the SATA Configuration Settings. An example of the SATA Configuration screen is shown below. SATA Controller(s) Enable or disable SATA device. SATA Mode Selection The SATA can be configured as a legacy IDE, RAID and AHCI mode. SATA Port 0~5 Display SATA device name string. Staggered Spin-up Appears when SATA mode is AHCI. AHCI supports staggered spin-up. Set this value to Enabled/Disabled.
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cPCI-6520 External SATA Port Appears when SATA mode is AHCI. eSATA port support. Set this value to Enabled/Disabled. Hot Plug Appears when SATA mode is AHCI. SATA port Hot Plug support. Set this value to Enabled/Disabled.
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8.3.6 Intel TXT(LT) Configuration You can use this screen to select options for the Intel TXT(LT) Configuration Settings. An example of the Intel TXT(LT) Configuration screen is shown below. Intel TXT(LT) Support Configurable when TPM is enabled, CPU supports SMX, Intel Virtualization Technology and VT-d when enabled. Set this value to Enabled/Disabled.
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cPCI-6520 8.3.7 AMT Configuration You can use this screen to select options for the AMT settings. Use the up and down < Arrow > keys to select an item. Use the < + > and < - > keys to change the value of the selected option. Intel AMT Intel AMT feature. Set this value to Enabled/Disabled. Un-configure ME Perform Management Engine un-configure without password operation. Set this value to Enabled/Disabled. Disable ME Temporary disable Management Engine. Set this value to Enabled/Disabled.
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8.3.8 USB Configuration You can use this screen to select options for the USB Configuration. Use the up and down < Arrow > keys to select an item. The screen is shown below. Legacy USB Support Enables legacy USB support. Auto option disables legacy support if no USB devices are connected. Disable option will keep USB devices available only for EFI applications. Set this value to Enabled/Disabled/Auto. USB 3.0 Support To enable or disable USB 3.0 (XHCI) controller support.
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cPCI-6520 EHCI Hand-off This is a workaround for OSes without EHCI hand-off support. The EHCI ownership change should be claimed by the EHCI driver. Set this value to Enabled/Disabled. 8.3.9 Super IO Configuration You can use this screen to select options for the Super IO settings. Use the up and down < Arrow > keys to select an item. Use the < + > and < - > keys to change the value of the selected option. The settings are described on the following pages. The screen is shown below.
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8.3.10 Hardware Monitor This option displays the current status of all of the monitored hardware devices/components such as voltages and temperatures. CPU Temperature Displays current CPU temperature. System Temperature Displays current system temperature. 3.3V Displays current system 3.3V voltage. 5V Displays current system 5V voltage. 12V Displays current system 12V voltage.
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cPCI-6520 8.3.11 Serial Port Console Redirection You can use this screen to select options for the serial port console redirection settings. Use the up and down < Arrow > keys to select an item. Use the < + > and < - > keys to change the value of the selected option. A description of the selected item appears on the right side of the screen. The settings are described on the following pages. An example of the Serial Port Console Redirection screen is shown below.
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Terminal Type VT100+ is the preferred terminal type for out-of-band management. Configuration options: VT100, VT100+, VT-UTF8, ANSI. Bits per second Select the bits per second you want the serial port to use for console redirection. The options are 115200, 57600, 38400, 19200, 9600. Data Bits Select the data bits you want the serial port to use for console redirection. Set this value to 7, 8. Parity Set this option to select Parity for console redirection.
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cPCI-6520 Flow Control Set this option to select Flow Control for console redirection. The settings for this value are None, Hardware RTS/CTS. VT-UTF8 Combo Key Support Enables VT-UTF8 combination key support for ANSI/VT100 terminals.Set this value to Enabled/Disabled. Recorder Mode When this mode is enabled, only text will be sent. This is to capture terminal data. Set this value to Enabled/Disabled. Resolution 100x31 Set this option to extended terminal resolution. Set this value to Enabled/Disabled.
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Out-of-Band Mgmt Port Microsoft Windows emergency management services (EMS) allows for remote management of a Windows Server OS through a serial port. Set this value to COM0, COM1, COM2 (Disabled), COM3 (Disabled) Terminal Type VT-UTF8 is the preferred terminal type for out-of-band management. The next best choice is VT100+ and then VT100. See above, in Console Redirection Settings page, for more Help with Terminal Type/Emulation. Configuration options: VT100, VT100+, VT-UTF8, ASNI.
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cPCI-6520 Parity This is a display-only function providing information about the parity for Out-of-Band Management. Stop Bits This is a display-only function providing information about the number of stop bits for Out-of-Band Management. 8.3.12 CPU PPM Configuration Processor Power Module (PPM) configuration parameters. EIST Enable or disable Intel SpeedStep. Set this value to Enabled/Disabled. Turbo Mode Set this option to enable or disable turbo mode . Set this value to Enabled/Disabled.
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CPU C3 Report Enable or disable CPU C3 (ACPI C2) report to OS. Set this value to Enabled/Disabled. CPU C6 Report Enable or disable CPU C6 (ACPI C3) report to OS. Set this value to Enabled/Disabled. CPU C7 Report Enable or disable CPU C7 (ACPI C3) report to OS. Set this value to Enabled/Disabled.
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cPCI-6520 8.4 Chipset Setup Select the Chipset tab from the setup screen to enter the Chipset BIOS Setup screen. You can select any of Chipset BIOS Setup options by highlighting it using the < Arrow > keys. The Chipset BIOS Setup screen is shown below. 8.4.1 PCH-IO Configuration PCH LAN Controller Enable or disable onchip NIC. Set this value to Enabled/Disabled HD Audio Enable or disable the onboard HDA controller. Set this value to Enabled/Disabled.
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PCI Express Configuration PCI Express Clock Gating Enable or disable XHCI Pre-Boot Driver support. Set this value to Enabled/Disabled. DMI Link ASPM Control Mode of operation of xHCI controller. Set this value to Enabled/ Disabled. Subtractive Decode Mode of operation of xHCI controller. Set this value to Enabled/ Disabled.
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cPCI-6520 USB Configuration XHCI Pre-Boot Driver Enable or disable XHCI Pre-Boot Driver support. Set this value to Enabled/Disabled. XHCI Mode Mode of operation of xHCI controller. Set this value to Enabled/ Disabled. HS Port #1/2/3/4 Switchable Allows for HS port switching between xHCI and EHCI. If disabled, port is routed to EHCI. If HS port is routed to xHCI, the corresponding SS port is enabled. Set this value to Enabled/ Disabled. xHCI Stream Enable or disable xHCI Maximum Primary Stream Array Size.
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EHCI1/2 Control the USB EHCI (USB 2.0) functions. One EHCI controller must always be enabled. Set this value to Enabled/Disabled. USB Ports Per-Port Disable Control Control the per-port disabling of USB ports 0~13. Set this value to Enabled/Disabled. 8.4.2 System Agent (SA) Configuration VT-d The Intel Virtualization Technology for Directed I/O. Set this value to Enabled/Disabled.
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cPCI-6520 Graphics Configuration Primary Display Select which graphics device should be the primary display. Set this value to Auto, IGFX, PCI. Internal Graphics Keep IGD enabled based on the setup options. Set this value to Auto, Enabled, Disabled. GTT Size Select the GTT size. Set this value to 1MB, 2MB. Aperture Size Select the aperture size. Set this value to 128MB, 256MB, 512MB.
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DVMT Pre-Allocated Select DVMT 5.0 Pre-Allocated (fixed) graphics memory size used by the internal graphics device. Configuration options as below: DVMT Total Gfx Memory Select DVMT 5.0 total graphic memory size used by the internal graphics device.
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cPCI-6520 Memory Configuration Memory Remap Enable or disable memory remap above 4G. Set this value to Enabled/Disabled.
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8.5 Boot Settings Select the Boot tab from the setup screen to enter the Boot BIOS Setup screen. You can select any of the items in the left frame of the screen, such as Boot Device Priority, to go to the sub menu for that item. You can display a Boot BIOS Setup option by highlighting it using the < Arrow > keys. The Boot Settings screen is shown below: Quiet Boot X Disabled - Set this value to allow the computer system to display the POST messages.
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cPCI-6520 Set Boot Priority Set Boot Option #1 ~2 boot priority. Hard Disk Drive BBS Priorities Specifies the boot device priority sequence from available hard drives. 8.5.1 CSM Parameter OpROM execution, boot option filter, etc. Launch CSM This option controls if CSM will be launched. Set this value to Always, Never. Boot option filter This option controls what devices system can boot to. Set this value to UEFI and Legacy, Legacy only, UEFI only.
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Launch Video OpROM policy This option controls the execution of UEFI and Legacy Video OpROM. Set this value to Do not launch, UEFI only, Legacy only. Other PCI device ROM priority For PCI devices other than Network, Mass storage or Video defines which OpROM to launch. Set this value to UEFI OpROM, Legacy OpROM.
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cPCI-6520 8.6 Security Setup Administrator, User Password If only the administrator's password is set, then this only limits access to setup and is only asked for when entering setup. If only the user's password is set, then this is a power on password and must be entered to boot or enter setup. In setup the user will have administrator rights.
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8.7 Save & Exit Menu Select the Save & Exit tab from the setup screen to enter the Save & Exit BIOS Setup screen. You can display an Exit BIOS Setup option by highlighting it using the < Arrow > keys. The Save & Exit BIOS Setup screen is shown below. Save Changes and Reset Reset the system after saving the changes.
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cPCI-6520 Discard Changes and Reset Reset system setup without saving any changes. Save Changes Save changes done so far to any of the setup options. Discard Changes Discard changes done so far to any of the setup options. Restore Changes Restore/Load Defaults values for all the setup options.
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Save as User Defaults Save the changes done so far as user defaults.. Restore User Defaults Save changes done so far to any of the setup options.
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cPCI-6520 9 Checkpoints & Beep Codes 9.1 Checkpoint Ranges Status Code Range Description 0x01 – 0x0B SEC execution 0x0C – 0x0F SEC errors 0x10 – 0x2F PEI execution up to and including memory detection 0x30 – 0x4F PEI execution after memory detection 0x50 – 0x5F PEI errors 0x60 – 0x8F DXE execution up to BDS 0x90 – 0xCF BDS execution 0xD0 – 0xDF DXE errors 0xE0 – 0xE8 S3 Resume (PEI) 0xE9 – 0xEF S3 Resume errors (PEI) 0xF0 – 0xF8 Recovery (PEI) 0xF9 – 0xFF Recovery errors (PEI) 9.
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Status Code Description 0x08 North Bridge initialization after microcode loading 0x09 South Bridge initialization after microcode loading 0x0A OEM initialization after microcode loading 0x0B Cache initialization SEC Error Codes 0x0C – 0x0D Reserved for future AMI SEC error codes 0x0E Microcode not found 0x0F Microcode not loaded SEC Beep Codes None PEI Phase Status Code Description Progress Codes 0x10 106 PEI Core is started 0x11 Pre-memory CPU initialization is started 0x12 Pre-mem
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cPCI-6520 Status Code Description 0x1A Pre-memory South Bridge initialization (South Bridge module specific) 0x1B Pre-memory South Bridge initialization (South Bridge module specific) 0x1C Pre-memory South Bridge initialization (South Bridge module specific) 0x1D – 0x2A OEM pre-memory initialization codes 0x2B Memory initialization. Serial Presence Detect (SPD) data reading 0x2C Memory initialization. Memory presence detection 0x2D Memory initialization.
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Status Code Description 0x3B Post-Memory South Bridge initialization is started 0x3C Post-Memory South Bridge initialization (South Bridge module specific) 0x3D Post-Memory South Bridge initialization (South Bridge module specific) 0x3E Post-Memory South Bridge initialization (South Bridge module specific) 0x3F-0x4E OEM post memory initialization codes 0x4F DXE IPL is started PEI Error Codes 0x50 Memory initialization error.
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cPCI-6520 Status Code Description 0xE3 OS S3 wake vector call 0xE4-0xE7 Reserved for future AMI progress codes S3 Resume Error Codes 0xE8 S3 Resume Failed 0xE9 S3 Resume PPI not Found 0xEA S3 Resume Boot Script Error 0xEB S3 OS Wake Error 0xEC-0xEF Reserved for future AMI error codes Recovery Progress Codes 0xF0 Recovery condition triggered by firmware (Auto recovery) 0xF1 Recovery condition triggered by user (Forced recovery) 0xF2 Recovery process started 0xF3 Recovery firmware imag
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PEI Beep Codes # of Beeps Description 1 Memory not Installed 1 Memory was installed twice (InstallPeiMemory routine in PEI Core called twice) 2 Recovery started 3 DXEIPL was not found 3 DXE Core Firmware Volume was not found 4 Recovery failed 4 S3 Resume failed 7 Reset PPI is not available DXE Phase Status Code 110 Description 0x60 DXE Core is started 0x61 NVRAM initialization 0x62 Installation of the South Bridge Runtime Services 0x63 CPU DXE initialization is started 0x64 CPU
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cPCI-6520 Status Code Description 0x6F North Bridge DXE initialization (North Bridge module specific) 0x70 South Bridge DXE initialization is started 0x71 South Bridge DXE SMM initialization is started 0x72 South Bridge devices initialization 0x73 South Bridge DXE Initialization (South Bridge module specific) 0x74 South Bridge DXE Initialization (South Bridge module specific) 0x75 South Bridge DXE Initialization (South Bridge module specific) 0x76 South Bridge DXE Initialization (South Bri
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Status Code Description 0xA0 IDE initialization is started 0xA1 IDE Reset 0xA2 IDE Detect 0xA3 IDE Enable 0xA4 SCSI initialization is started 0xA5 SCSI Reset 0xA6 SCSI Detect 0xA7 SCSI Enable 0xA8 Setup Verifying Password 0xA9 Start of Setup 0xAA Reserved for ASL (see ASL Status Codes section below) 0xAB Setup Input Wait 0xAC Reserved for ASL (see ASL Status Codes section below) 0xAD Ready To Boot event 0xAE Legacy Boot event 0xAF Exit Boot Services event 0xB0 Runtime Set
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cPCI-6520 Status Code Description 0xD3 Some of the Architectural Protocols are not available 0xD4 PCI resource allocation error.
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ACPI/ASL Checkpoints Status Code Description 0x01 System is entering S1 sleep state 0x02 System is entering S2 sleep state 0x03 System is entering S3 sleep state 0x04 System is entering S4 sleep state 0x05 System is entering S5 sleep state 0x10 System is waking up from the S1 sleep state 0x20 System is waking up from the S2 sleep state 0x30 System is waking up from the S3 sleep state 0x40 System is waking up from the S4 sleep state 0xAC System has transitioned into ACPI mode.
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cPCI-6520 Important Safety Instructions For user safety, please read and follow all instructions, WARNINGS, CAUTIONS, and NOTES marked in this manual and on the associated equipment before handling/operating the equipment. X Read these safety instructions carefully. X Keep this user’s manual for future reference. X Read the specifications section of this manual for detailed information on the operating environment of this equipment.
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X Never attempt to fix the equipment. Equipment should only be serviced by qualified personnel. A Lithium-type battery may be provided for uninterrupted, backup or emergency power. WARNING: X 116 Risk of explosion if battery is replaced with one of an incorrect type. Dispose of used batteries appropriately.
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cPCI-6520 Getting Service Contact us should you require any service or assistance. ADLINK Technology, Inc. Address: 9F, No.166 Jian Yi Road, Zhonghe District New Taipei City 235, Taiwan ᄅ‫ؑק‬խࡉ೴৬ԫሁ 166 ᇆ 9 ᑔ Tel: +886-2-8226-5877 Fax: +886-2-8226-5717 Email: service@adlinktech.com Ampro ADLINK Technology, Inc. Address: 5215 Hellyer Avenue, #110 San Jose, CA 95138, USA Tel: +1-408-360-0200 Toll Free: +1-800-966-5200 (USA only) Fax: +1-408-360-0222 Email: info@adlinktech.com ADLINK Technology (China) Co.
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ADLINK Technology, Inc. (French Liaison Office) Address: 6 allée de Londres, Immeuble Ceylan 91940 Les Ulis, France Tel: +33 (0) 1 60 12 35 66 Fax: +33 (0) 1 60 12 35 66 Email: france@adlinktech.com ADLINK Technology Japan Corporation Address: ͱ101-0045 ᵅҀ䛑गҷ⬄ऎ⼲⬄䤯‫ ⬎ފ‬3-7-4 ⼲⬄ 374 ɛɳ 4F KANDA374 Bldg. 4F, 3-7-4 Kanda Kajicho, Chiyoda-ku, Tokyo 101-0045, Japan Tel: +81-3-4455-3722 Fax: +81-3-5209-6013 Email: japan@adlinktech.com ADLINK Technology, Inc.