User Manual

ManualsBrandsADLINK ManualsHardwareCoreModule 720

CoreModule

720

Single Board Computer

Reference Manual

P/N 50-1Z105-1020

Summary of content (62 pages)

PAGE 1
CoreModule® 720 Single Board Computer Reference Manual P/N 50-1Z105-1020
PAGE 2
Notice Page DISCLAIMER ADLINK Technology, Incorporated makes no representations or warranties with respect to the contents of this manual or of the associated ADLINK products, and specifically disclaims any implied warranties of merchantability or fitness for any particular purpose. ADLINK shall under no circumstances be liable for incidental or consequential damages or related expenses resulting from the use of this product, even if it has been notified of the possibility of such damages.
PAGE 3
Contents Chapter 1 About This Manual ....................................................................................................1 Purpose of this Manual ....................................................................................................................1 References ......................................................................................................................................1 Chapter 2 Product Overview...........................................................
PAGE 4
Contents Serial Console ........................................................................................................................ 34 Serial Console Setup ......................................................................................................... 34 Hot (Serial) Cable .............................................................................................................. 34 Temperature Monitoring .............................................................................
PAGE 5
Contents List of Tables Table 2-1. Table 2-2. Table 2-3. Table 2-4. Table 2-5. Table 2-6. Table 2-7. Table 3-1. Table 3-2. Table 3-3. Table 3-4. Table 3-5. Table 3-6. Table 3-7. Table 3-8. Table 3-9. Table 3-10. Table 3-11. Table 3-12. Table 3-13. Table 3-14. Table 3-15. Table 3-16. Table 3-17. Table 3-18. Table 3-19. Table 3-20. Table 3-21. Table 4-1. Table A-1. Table B-1. CoreModule 720 Major Component Descriptions and Functions ........................................................
PAGE 6
Contents vi Reference Manual CoreModule 720
PAGE 7
Chapter 1 About This Manual Purpose of this Manual This manual is for designers of systems based on the CoreModule® 720 Single Board Computer (SBC). This manual contains information that permits designers to create an embedded system based on specific design requirements.
PAGE 8
Chapter 1 About This Manual Chip Specifications The following integrated circuits (ICs) are used in the CoreModule 720 single board computer: • Intel Corporation and the Atom™ E6XXT processors Data sheet: http://download.intel.com/embedded/processor/datasheet/324208.pdf • Micron Technology, Inc. and the MT47H256M8EB-25E DDR2 on-board System Memory Web site: http://www.micron.
PAGE 9
Chapter 2 Product Overview This overview presents information about the PC/104 architecture and the CoreModule 720 Single Board Computer (SBC). After reading this chapter you should understand: • PC/104 architecture • Product description • Major components (ICs) • Headers, Connectors, and Sockets • Specifications PC/104 Architecture The PC/104 architecture affords a great deal of flexibility in system design.
PAGE 10
Chapter 2 Product Overview Screws (4) PC/104 Module 0.6 inch Spacers (4) PC/104-Plus Module ISA Bus Expansion Stackthrough Connectors PCI Stackthrough Connectors 0.6 inch Spacers (4) CoreModule 720 CM720stackthru_a PCI Stackthrough Connectors 0.6 inch Spacers (4) Nuts (4) or Chassis Standoffs Figure 2-1.
PAGE 11
Chapter 2 Product Overview Module Features • • • • • • CPU  Provides a 600MHz, 1.3GHz, or 1.
PAGE 12
Chapter 2 • • • USB Interface  Provides three root USB hubs  Provides up to six USB ports  Supports USB boot devices  Supports USB Keyboard and Mouse  Supports USB v2.0 EHCI and v1.1 UHCI  Supports over-current detection status Ethernet Interface  Provides one fully independent Ethernet port  Provides integrated LEDs on each port (Link/Activity and Speed)  Provides one Intel 82574IT controller chip  Provides header for LAN LED signals (Gigabit only)  Supports IEEE 802.
PAGE 13
Chapter 2  Product Overview Logo Screen (Splash) Block Diagram Figure 2-2 shows the functional components of the CoreModule 720. Memory Bus 4x DDR2 System Memory 1 4x DDR2 System Memory 2 LVDS Header SDVO Connector SMBus Header SMBus CPU Intel Atom E620T, E660T, or E680T (600MHz, 1.3GHz, or 1.
PAGE 14
Chapter 2 Product Overview Major Component (ICs) Definitions Table 2-1 lists the major ICs, including a brief description of each, on the CoreModule 720. Figures 2-3 and 2-4 show the locations of the major ICs. Table 2-1. Major Component Descriptions and Functions 8 Chip Type Mfg. Model Description CPU (U1) Intel Atom E620T, E660T, or E680T 600MHz, 1.3GHz, Integrates or 1.
PAGE 15
Chapter 2 Product Overview Table 2-1.
PAGE 16
Chapter 2 Product Overview T1 U5 U15 U4 U1 U16 U3 CM720_Top_Comp_a U33 Key: U1 - CPU U2 - DDR2 SDRAM - 1 U3 - DDR2 SDRAM - 1 U4 - DDR2 SDRAM - 1 U5 - DDR2 SDRAM - 1 U10 - PCH U15 - Gigabit Ethernet Controller U16 - Ethernet EEPROM U18 - PCIe to PCI Bridge U21 - RS-232 Transceiver - COM0 U22 - RS-232 Transceiver - COM1-3 U31 - SPI Flash - BIOS U33 - Temperature Monitor U35 - Thermal Regulator - SSD T1 - Gigabit Ethernet Transformer U2 U31 U35 U10 U18 U22 U21 Figure 2-3.
PAGE 17
Chapter 2 Product Overview Header, Connector, and Socket Definitions Table 2-2 describes the headers, connectors, and socket of the CoreModule 720 shown in Figure 2-6. Table 2-2. Module Header and Connector Descriptions Header # Board Access Description J1 – LPC Debug Top 10-pin, 0.050" (1.27mm) female debug port header for issues such as Port 80 POST errors (NELTRON, 2200SB-10G-SM-23-CR) J3 – GPIO Top 10-pin, 0.
PAGE 18
Chapter 2 Product Overview Table 2-2. Module Header and Connector Descriptions (Continued) J22 – Utility Top 5-pin, 0.100" (2.54mm) single-row header for Power Button, Reset Switch, and Speaker signals (SAMTEC, HMTSW-105-08-LM-S-300) J23 – LVDS Top 20-pin, 0.079" (2mm) shrouded header for LVDS video signals (HIROSE, DF11-20DP-2DSA) J24 – SMBus Top 5-pin, 0.
PAGE 19
Chapter 2 Product Overview J1 J8 J23 J15 J9 JP3 J7 J21 J19 ABCD J17 CM720_Top_Conn_a Key: J1 - LPC J3 - GPIO J4 - CAN J5 - SD Memory Socket - Bottom J6 - I2C J7 - SATA0 J8 - Ethernet - Gigabit J9 - Ethernet LED - Gigabit J10 - Serial 1 - COM 0 J11 - Serial 2 - COM 1, 2, 3 AB J12 - USB 0, 1 J13 - USB 4, 5 J14 - USB 2, 3 J15 - SDVO J17 - PC/104-Plus J18 - PC/104 DC J19 - Power J20 - Battery J21 - Fan J22 - Utility J23 - LVDS J24 - SMBus JP1 - RTC Reset (See jumper table) JP3 - LVDS Voltage Select
PAGE 20
Chapter 2 Product Overview Key: JP1 - Clear CMOS JP3 - LVDS Voltage Select CM720_Top_Jmpr_a JP3 JP1 Figure 2-7. Jumper Header Locations (Top Side) Specifications Physical Specifications Table 2-4 provides the physical dimensions of the CoreModule 720. Table 2-4. Weight and Footprint Dimensions 14 NOTE Item Dimension Weight 0.12 kg (0.25 lbs) Height (overall) 11.05 mm (0.435 inches) Board thickness 2.362 mm (0.093 inches) Width 96.01 mm (3.78 inches) Length 115.57 mm (4.
PAGE 21
Chapter 2 Product Overview 0.33 (8.38mm) 0.20 (5.08mm) 0.00 1.95 (49.53mm) 3.78 (96.01mm) 3.58 (90.93mm) 3.45 (87.63mm) Mechanical Specifications 4.05 (102.87mm) 3.55 (90.17mm) 3.35 (85.09mm) 3.55 (90.17mm) CM720_Top_Dmn_a 3.20 (81.28mm) 1.38 (35.05mm) 0.30 (7.62mm) 0.20 (5.08mm) 0.00 0.00 0.50 (12.70mm) 0.50 (12.70mm) Figure 2-8. Mechanical Overview (Top Side) NOTE CoreModule 720 All dimensions are given in inches. Black square pins on headers and connectors represent pin 1.
PAGE 22
Chapter 2 Product Overview Power Specifications Table 2-5 provides the current measurements for the CoreModule 720. Table 2-5. Power Supply Requirements Parameter 600MHz E620T Characteristics 1.3GHz E660T Characteristics 1.6GHz E680T Characteristics Input Type Regulated DC voltages Regulated DC voltages Regulated DC voltages In-rush Peak Current and Duration See Figure 2-9 See Figure 2-9 See Figure 2-9 Typical Idle Current 1.67A (8.34W) 1.69A (8.43W) 1.67A (8.33W) BIT Current 2.72A (13.
PAGE 23
Chapter 2 Product Overview Environmental Specifications Table 2-6 provides the most efficient operating and storage condition ranges required for this module. Table 2-6.
PAGE 24
Chapter 2 Product Overview Thermal/Cooling Requirements The CPU is the primary source of heat on the board. The CoreModule 720 is designed to operate at the maximum speed of the CPU and requires a cooling solution (available option). See Table 2-7 for optional cooling solution temperature qualifications. Figure 2-10 depicts height measurements of the optional cooling assemblies. Table 2-7.
PAGE 25
Chapter 3 Hardware Overview This chapter discusses the chips and connectors of the module features in the following order: • CPU • Graphics • Memory • Interrupt Channel Assignments • Memory Map • I/O Address Map • Serial Port Interfaces • USB Interfaces • Ethernet Interface • Video Interfaces  LVDS  SDVO (Supports VGA as described in Appendix B, “Video Adapter Board ” ) • Power Interface • GPIO Interface • Utility Interface  Power Button  Reset Switch  Speaker • SM
PAGE 26
Chapter 3 Hardware NOTE ADLINK Technology, Inc. only supports the features and options listed in this manual. The main components used on the CoreModule 720 may provide more features or options than are listed in this manual. Some of these features and options are not supported on the module and will not function as specified in the chip documentation. The pin-out tables only of non-standard headers and connectors are included in this chapter.
PAGE 27
Chapter 3 Hardware Interrupt Channel Assignments The interrupt channel assignments are shown in Table 3-1. Table 3-1. Interrupt Channel Assignments Device vs IRQ No.
PAGE 28
Chapter 3 Hardware I/O Address Map Table 3-3 shows the I/O address map. These are DOS-level addresses. The OS typically hides these physical addresses by way of memory management. Table 3-3.
PAGE 29
Chapter 3 Hardware Serial Interfaces The CoreModule 720 provides four RS-232 serial ports. The PCH EG20T contains the circuitry for all four serial ports and delivers the signals through two RS-232 transceivers: one transceiver for port COM0 and the second transceiver for ports COM1, COM2, and COM3.
PAGE 30
Chapter 3 Hardware Table 3-5 describes the pin signals of the serial 2 header (J11), which consists of 10 pins, two rows, odd/even (1, 2) pin sequence, and 0.079" (2mm) pitch Table 3-5. Serial 2 (COM1, 2, and 3) Interface Pin Signal Descriptions (J11) Pin # Signal DB9 Pin # Description 1 S1_TXD 3 COM1 Transmit Data – Serial port transmit data output is typically held to a logic 1 when no data is being sent.
PAGE 31
Chapter 3 Hardware Table 3-6. USB0 and USB1 Interface Pin Signals (J12) (Continued) 9 USB_GND0 USB0 Ground 10 USB_GND1 USB1 Ground Note: The shaded table cells denote power or ground. Table 3-7 describes the pin signals of the USB2 and USB3 header, which consists of 10 pins in two rows, with odd/even (1, 2) pin sequence, and 0.079" (2mm) pitch. Table 3-7.
PAGE 32
Chapter 3 Hardware Ethernet Interface The CoreModule 720 supports one Gigabit Ethernet interface. The Ethernet interface is implemented from the 82574IT Ethernet controller and provides one GLAN interface, which occupies PCI Express port 2. The Ethernet function supports multi-speed operation at 10/100/1000 Mbps and operates in full-duplex at all supported speeds or half duplex at 10/100 Mbps while adhering to the IEEE 802.3x flow control specification.
PAGE 33
Chapter 3 Hardware Video (SDVO/LVDS) Interfaces The Atom™ E6XXT CPU provides an integrated 2D/3D graphics engine, which supports video decode such as MPEG2, MPEG4, VC1, WMV9, H.264 (main, baseline at L3 and High-profile level 4.0/4.1), and DivX* as well as video encode such as MPEG4, H.264 (baseline at L3), and VGA. The CPU supports LVDS and SDVO display ports, permitting simultaneous, independent operation of two displays. The video interface features are listed in the following bullets.
PAGE 34
Chapter 3 Hardware Table 3-10. SDVO Interface Pin Signals (J15) (Continued) Pin # Signal Description 20 SDVO_I2C_CLK I2C control signal (Clock) for SDVO device 21 SDVO_I2C_DAT I2C control signal (Data) for SDVO device 22 RESET Reset signal 23 +3.3V_1 +3.3 Volt Power 1 24 +2.5V +2.5 Volt Power 25 +5V_1 +5 Volt Power 1 26 GND8 Ground 8 27 SDVO_TVCLKIN- SDVO TV-Out Synchronization Clock Input - Negative 28 SDVO_TVCLKIN+ SDVO TV-Out Synchronization Clock Input - Positive 29 +3.
PAGE 35
Chapter 3 Hardware Power Interface The CoreModule 720 requires one +5 volt DC power source and provides a shrouded 10-pin, right-angle header with 2 rows, odd/even pin sequence (1, 2), and 0.100" (2.54mm) pitch. If the +5VDC power drops below ~4.65V, a low voltage reset is triggered, resetting the system. The power input header (J19) supplies the following voltage and ground directly to the module: • 5.0VDC +/- 5% Table 3-12.
PAGE 36
Chapter 3 Hardware Utility Interface The Utility interface provides three I/O signals on the module and consists of a 5-pin, 0.100" (2.54mm), single-row header (J22). The E6XXT CPU drives the Power Button and Speaker signals on the Utility interface. A separate Power Management microprocessor drives the Reset Switch signal. Table 3-14 provides the signal definitions.
PAGE 37
Chapter 3 Hardware System Management Bus (SMBus) The E6XXT chip contains a host SMBus port. The host port allows the CPU access to the SMBus slave through header, J24. The SMBus slave includes the CPU Temperature Monitor. Table 3-15 lists the device name and corresponding reserved binary address on the SMBus. Table 3-16 lists the SMBus pin signals on 5 pins, 1 row, 0.079" (2mm) pitch. Table 3-15. SMBus Reserved Addresses Component Address (Hex) CPU Temperature Monitor 4C Table 3-16.
PAGE 38
Chapter 3 Hardware I2C Interface The CoreModule 720 provides a single-channel I2C interface, which conforms to version 2.1 of the I2C bus specification. The I2C controller resides on the EG20T PCH and operates as a master or slave device, supporting a multi-master bus. The following list highlights the features of the I2C bus interface.
PAGE 39
Chapter 3 Hardware Battery Table 3-20 lists the pin signals of the External Battery Input header for backup RTC (Real Time Clock), which uses 2 pins with 0.049" (1.25mm) pitch. Table 3-20. External Battery Input Header (J20) Pin # Signal Description 1 VBAT_EXT +3.0 volts DC 2 GND Ground Note: The shaded table cells denote power or ground. The RTC pin has an expected current draw of ~36A at room temperature. The battery is used only when power is not applied to the board.
PAGE 40
Chapter 3 Hardware Oops! Jumper (BIOS Recovery) The Oops! jumper function is provided in the event the BIOS settings you have selected prevent you from booting the system. By using the Oops! jumper you can prevent the current BIOS settings in flash from being loaded, allowing you to boot using default settings. Use a jumper to connect the DTR pin (4) to the RI pin (9) on Serial Port 1 (COM0) prior to boot up to prevent the present BIOS settings from loading.
PAGE 41
Chapter 3 Hardware Watchdog Timer The Watchdog Timer (WDT) restarts the system if a mishap occurs, ensuring proper start up after the interruption. Possible problems include failure to boot properly, the application software’s loss of control, failure of an interface device, unexpected conditions on the bus, or other hardware or software malfunctions. The WDT (Watchdog Timer) can be used both during the boot process and during normal system operation.
PAGE 42
Chapter 3 36 Hardware Reference Manual CoreModule 720
PAGE 43
Chapter 4 BIOS Setup Introduction This section assumes the user is familiar with general BIOS Setup and does not attempt to describe the BIOS functions. Refer to “BIOS Setup Menus ” on page 39 in this chapter for a map of the BIOS Setup settings. If ADLINK has added to or modified any of the standard BIOS functions, these functions will be described. Entering BIOS Setup (Local Video Display) To enter BIOS Setup using a local video display for the CoreModule 720: 1.
PAGE 44
Chapter 4 BIOS Setup 8. Restore power to the CoreModule 720. 9. Press the F2 key to enter Setup (early in the boot sequence if Fast Boot is set to [Enabled].) If Fast Boot is set to [Enabled], you may never see the screen prompt. 10. Use the key to select the screen menus listed in the Opening BIOS screen. NOTE The serial console port is not hardware protected. Diagnostic software that probes hardware addresses may cause a loss or failure of the serial console functions.
PAGE 45
Chapter 4 BIOS Setup BIOS Setup Menus This section provides illustrations of the six main setup screens in the CoreModule 720 BIOS Setup Utility. Below each illustration is a bullet list of the screen’s submenus and setting selections. The setting selections are presented in brackets after each submenu or menu item, and the optimal default settings are presented in bold. For more detailed definitions of the BIOS settings, refer to the AMI Aptio TSE User Manual: http://www.ami.
PAGE 46
Chapter 4 BIOS Setup • System Language • System Date [English] System Date (day of week, mm:dd:yyyy) – This field requires the alpha-numeric entry of the day of week, day of the month, calendar month, and all 4 digits of the year, indicating the century plus year (Fri XX/XX/20XX). • System Time System Time (hh:mm:ss) – This is a 24-hour clock setting in hours, minutes, and seconds. Advanced BIOS Setup Screen Aptio Setup Utility - Copyright (C) 20XX American Megatrends, Inc.
PAGE 47
Chapter 4   • BIOS Setup • VGA Palette Snoop [Disabled; Enabled] • PERR# Generation [Disabled; Enabled] • SERR# Generation [Disabled; Enabled] PCI Express Device Settings • Relaxed Ordering [Disabled; Enabled] • Extended Tag [Disabled; Enabled] • No Snoop [Disabled; Enabled] • Maximum Payload [Auto; 128 Bytes; 256 Bytes; 512 Bytes; 1024 Bytes; 2048 Bytes; 4096 Bytes] • Maximum Read Request [Auto; 128 Bytes; 256 Bytes; 512 Bytes; 1024 Bytes; 2048 Bytes; 4096 Bytes] PCI Express Link Set
PAGE 48
Chapter 4 • SDIO Configuration  • • BIOS Setup SDIO Access Mode [Auto; DMA; PIO] Thermal Configuration  Critical Trip Point [POR; 30 C; 40 C; 50 C; 60 C; 70 C; 80 C; 90 C; 95 C]  Active Trip Point [Disabled; 30 C; 40 C; 50 C; 60 C; 70 C; 80 C; 90 C; 95 C; 100 C]  Passive Trip Point [Disabled; 30 C; 40 C; 50 C; 60 C; 70 C; 80 C; 90 C; 95 C; 100 C] • Passive TC1 Value [1] • Passive TC2 Value [5] • Passive TSP Value [10]  Thermal Offset [Disabled; Enabled]  DTS Calibration [Disabled;
PAGE 49
Chapter 4 BIOS Setup • Console Redirection Settings - Terminal Type [VT100; VT100+; VT-UTF8; ANSI] - Bits per second [9600; 19200; 38400; 57600; 115200] - Data Bits [7; 8] - Parity [None; Even; Odd; Mark; Space] - Stop Bits [1; 2] - Flow Control [None; Hardware RTS/CTS] - Recorder Mode [Disabled; Enabled] - Resolution 100x31 [Disabled; Enabled] - Legacy OS Redirection [80x24; 80x25] - PuTTY Keypad [VT100; LINUX; XTERMR6; SCO; ESCN; VT400] - Redirection After BIO [Always Enable; BootLoader] NOTE The ser
PAGE 50
Chapter 4 • BIOS Setup North Bridge Chipset Configuration   Memory Information • MRC Version XX.
PAGE 51
Chapter 4 BIOS Setup • IOH Configuration • GPIO Configuration  GPIO 0 [Disabled; Enabled]  GPIO 1 [Disabled; Enabled]  GPIO 2 [Disabled; Enabled]  GPIO 3 [Disabled; Enabled]  GPIO 4 [Disabled; Enabled]  GPIO 5 [Disabled; Enabled]  GPIO 6 [Disabled; Enabled]  GPIO 7 [Disabled; Enabled] Boot BIOS Setup Screen Aptio Setup Utility - Copyright (C) 20XX Amreican Megatrends, Inc.
PAGE 52
Chapter 4 • • BIOS Setup CSM16 Module Version XX.
PAGE 53
Chapter 4 BIOS Setup Save & Exit BIOS Setup Screen Aptio Setup Utility - Copyright (C) 20XX American Megatrends, Inc. Main Advanced Chipset Boot Security Save & Exit Save Changes and Exit Discard Changes and Exit Save Changes and Reset Discard Changes and Reset [Setting Description] Save Options Save Changes Discard Changes Restore Defaults Save as User Defaults Restore User Defaults : : Select Screen Select Item Enter : Select +/- : Change Opt.
PAGE 54
Chapter 4  BIOS Setup Save as User Defaults •  Restore User Defaults • • Restore User Defaults? [Yes; No] Boot Override  P1-GLS85LS1032A CS 32GBN A101C0 •  Save configuration and reset? [Yes; No] Built-in EFI Shell NOTE 48 Save configuration? [Yes; No] Selecting this setting enters the system into the EFI Shell mode screen.
PAGE 55
Appendix A Technical Support ADLINK Technology, Inc. provides a number of methods for contacting Technical Support listed below in Table A-1. Requests for support through the Ask an Expert are given the highest priority, and usually will be addressed within one working day. • ADLINK’s Ask an Expert – This is a comprehensive support center designed to meet all your technical needs. This service is free and available 24 hours a day through the Ampro By ADLINK web page at http://www.adlinktech.com/AAE/.
PAGE 56
Appendix A Technical Support Table A-1. Technical Support Contact Information (Continued) Standard Mail ADLINK Technology Beijing Address: ࣫ҀᏖ⍋⎔ऎϞഄϰ䏃 1 োⲜ߯ࡼ࡯໻ॺ E ᑻ 801 ᅸ(100085) Rm. 801, Power Creative E, No. 1, Shang Di East Rd., Beijing, 100085 China Tel: +86-10-5885-8666 Fax: +86-10-5885-8626 Email: market@adlinktech.com ADLINK Technology Shenzhen Address: ⏅ഇᏖफቅऎ⾥ᡔುफऎ催ᮄफϗ䘧 ᭄ᄫᡔᴃು A1 ᷟ 2 ὐ C ऎ (518057) 2F, C Block, Bldg. A1, Cyber-Tech Zone, Gao Xin Ave. Sec. 7, High-Tech Industrial Park S.
PAGE 57
Appendix A Technical Support Table A-1. Technical Support Contact Information (Continued) Standard Mail ADLINK Technology, Inc. (Israeli Liaison Office) Address: 6 Hasadna St., Kfar Saba 44424, Israel Tel: +972-9-7446541 Fax: +972-9-7446542 Email: israel@adlinktech.
PAGE 58
Appendix A 52 Technical Support Reference Manual CoreModule 720
PAGE 59
Appendix B Video Adapter Board Overview This appendix describes the functionality and features of the CoreModule 720 video adapter board and presents an illustration of the connector locations and the board dimensions as well as the pin-out table for the non-standard VGA interface on the adapter. Product Description The video adapter board enables VGA functionality on the CoreModule 720, converting digital RGB input from the module’s SDVO port to analog RGB output through an on-board display controller.
PAGE 60
Appendix B Video Adapter Board Video Adapter Board Header Signals The following table defines the pin signals of the non-standard VGA header on the video adapter board. This appendix does not define the industry-standard SDVO connector on the board. See Table 2-2 on page 11 for more SDVO connector information. Table B-1 lists the signals and their descriptions for the J2 VGA interface, which provides a shrouded, 12-pin right-angle header with odd/even (1, 2) pin sequence, and 0.
PAGE 61
Index A Advanced BIOS setup screen ............................. 40 AMI BIOS Aptio TSE User’s Guide .................... 1 ANSI-compatible serial terminal ........................ 34 Ask an Expert ..................................................... 49 Atom E6XXT CPU ......................................... 4, 20 expansion buses features .............................................................5 specification references ...................................1 F fan interface signal descriptions .......
PAGE 62
Index O OEM Logo description ..................................................... 38 feature .............................................................. 7 Oops! Jumper (BIOS recovery) description ..................................................... 34 feature .............................................................. 6 P PC/104 Architecture ............................................. 3 PCH specification reference ................................. 2 PCI specification reference ..................