User`s manual

12 • Introduction
1.3.11 IEEE-1284 Parallel Port/Printer Interface
The parallel I/O interface signals are routed to the DB-25 connector on the
front faceplate. This port supports the full IEEE-1284 specification and
provides a basic printer interface. The BIOS will initialize the parallel port as
LPT1 with an ISA I/O base address of 378h. This default configuration also
assigns the parallel port to IRQ7. The printer interface mode (Normal,
Extended, EPP, or ECP) is selectable through the BIOS menu.
1.3.12 Power Ramp Circuitry
The PXD-3710/3710F features a power controller with power ramp circuitry
to allow the board’s voltages to be ramped in a controlled manner. The power
ramp circuitry eliminates any large voltage or current spikes caused by hot
swapping boards. This controlled ramping is a requirement of the
CompactPCI Hot Swap specification, PICMG 2.1, Version 1.0. The
PXD-3710’s power controller unconditionally resets the board when it detects
that the 3.3V, 5V, and 12V supplies are below an acceptable operating limit:
3.0V (3.3V supply), 4.75V (5V supply), and 10.0V (+12V supply).
1.3.13 Watchdog Timer
The watchdog timer optionally monitors system operation and can be
programmed for different timeout periods (from 1 to 255 seconds or 1 to 255
minutes). It is a two-stage watchdog, meaning that it can be enabled to
produce a non-maskable interrupt (NMI) or a “CPU init” before it generates a
reset. Failure to strobe the watchdog timer within the programmed time
period may result in an NMI, a reset request, or both. A register bit can be
enabled to indicate if the watchdog timer caused the reset event. This
watchdog timer register is cleared on power-up, enabling system software to
take appropriate action if the watchdog generates the reboot. See Section
5.1, “Watchdog Timer Overview,” for more information, including sample
code.