Specifications

Chapter 2. Architecture and technical overview 47
򐂰 No off-chip driver or receivers
Removing drivers or receivers from the L3 access path lowers interface requirements,
conserves energy, and lowers latency.
򐂰 Small physical footprint
The performance of eDRAM when implemented on-chip is similar to conventional SRAM
but requires far less physical space. IBM on-chip eDRAM uses only a third of the
components used in conventional SRAM, which has a minimum of six transistors to
implement a 1-bit memory cell.
򐂰 Low energy consumption
The on-chip eDRAM uses only 20% of the standby power of SRAM.
2.1.7 POWER7 processor and Intelligent Energy
Energy consumption is an important area of focus for the design of the POWER7 processor,
which includes Intelligent Energy features that help to dynamically optimize energy usage
and performance so that the best possible balance is maintained. Intelligent Energy features
like EnergyScale work with IBM Systems Director Active Energy Manager to dynamically
optimize processor speed based on thermal conditions and system utilization.
2.1.8 Comparison of the POWER7 and POWER6 processors
Table 2-2 shows comparable characteristics between the generations of POWER7 and
POWER6 processors.
Table 2-2 Comparison of technology for the POWER7 processor and the prior generation
POWER7 POWER6+ POWER6
Technology 45 nm 65 nm 65 nm
Die size 567 mm
2
341 mm
2
341 mm
2
Maximum cores 822
Maximum SMT
threads per core
4 threads 2 threads 2 threads
Maximum frequency 4.25 GHz 5.0 GHz 4.7 GHz
L2 Cache 256 KB per core 4 MB per core 4 MB per core
L3 Cache 4 MB of FLR-L3 cache
per core with each core
having access to the full
32 MB of L3 cache,
on-chip eDRAM
32 MB off-chip eDRAM
ASIC
32 MB off-chip eDRAM
ASIC
Memory support DDR3 DDR2 DDR2
I/O bus Two GX++ One GX++ One GX++
Enhanced cache
mode (TurboCore)
Ye s
a
a. Not supported on the Power 770 and Power 780 4-socket systems.
No No
Sleep and nap mode
b
Both Nap only Nap only