Specifications

42 IBM Power 770 and 780 Technical Overview and Introduction
Table 2-1 summarizes the technology characteristics of the POWER7 processor.
Table 2-1 Summary of POWER7 processor technology
2.1.2 POWER7 processor core
Each POWER7 processor core implements aggressive out-of-order (OoO) instruction
execution to drive high efficiency in the use of available execution paths. The POWER7
processor has an Instruction Sequence Unit that is capable of dispatching up to six
instructions per cycle to a set of queues. Up to eight instructions per cycle can be issued to
the instruction execution units. The POWER7 processor has a set of 12 execution units:
򐂰 Two fixed point units
򐂰 Two load store units
򐂰 Four double precision floating point units
򐂰 One vector unit
򐂰 One branch unit
򐂰 One condition register unit
򐂰 One decimal floating point unit
These caches are tightly coupled to each POWER7 processor core:
򐂰 Instruction cache: 32 KB
򐂰 Data cache: 32 KB
򐂰 L2 cache: 256 KB, implemented in fast SRAM
Technology POWER7 processor
Die size 567 mm
2
Fabrication technology 򐂰 45 nm lithography
򐂰 Copper interconnect
򐂰 Silicon-on-Insulator
򐂰 eDRAM
Components 1.2 billion components/transistors offering the
equivalent function of 2.7 billion (For further details see
2.1.6, “On-chip L3 cache innovation and Intelligent
Cache” on page 46.)
Processor cores 4, 6, or 8
Max execution threads core/chip 4/32
L2 cache core/chip 256 KB/2 MB
On-chip L3 cache core/chip 4 MB/32 MB
DDR3 memory controllers 1 or 2
SMP design-point 32 sockets with IBM POWER7 processors
Compatibility With prior generation of POWER processor