Specifications

Chapter 2. Architecture and technical overview 41
Figure 2-3 shows the POWER7 processor die layout with the major areas identified:
򐂰 Processor cores
򐂰 L2 cache
򐂰 L3 cache and chip interconnection
򐂰 Simultaneous multiprocessing (SMP) links
򐂰 Memory controllers.
Figure 2-3 POWER7 processor die with key areas indicated
2.1.1 POWER7 processor overview
The POWER7 processor chip is fabricated using the IBM 45 nm Silicon-On-Insulator (SOI)
technology using copper interconnect and implements an on-chip L3 cache using eDRAM.
The POWER7 processor chip is 567 mm
2
and is built using 1.2 billion components
(transistors). Eight processor cores are on the chip, each with 12 execution units, 256 KB of
L2 cache, and access to up to 32 MB of shared on-chip L3 cache.
For memory access, the POWER7 processor includes two DDR3 (double data rate 3)
memory controllers, each with four memory channels. To be able to scale effectively, the
POWER7 processor uses a combination of local and global SMP links with very high
coherency bandwidth and takes advantage of the IBM dual-scope broadcast coherence
protocol.