Specifications

76 •• 8254 Programmable Interval Time
A.2 The Control Byte
The 8254 occupies 8 I/O address locations in the PCI-7200 I/O
map. As shown below.
Base + 0 LSB OR MSB OF COUNTER 0
Base + 4 LSB OR MSB OF COUNTER 1
Base + 8 LSB OR MSB OF COUNTER 2
Base + C CONTROL BYTE for Chip 0
Before loading or reading any of these individual counters, the
control byte (Base + C) must be loaded first. The format of control
byte is :
Control Byte : (Base + 7, Base + 11)
Bit 7 6 5 4 3 2 1 0
SC1 SC0 RL1 RL0 M2 M1 M0 BCD
• SC1 & SC1 - Select Counter (Bit7 & Bit 6)
SC1 SC0 COUNTER
0 0 0
0 1 1
1 0 2
1 1 ILLEGAL
• RL1 & RL0 - Select Read/Load operation (Bit 5 & Bit 4)
RL1 RL0 OPERATION
0 0 COUNTER LATCH
0 1 READ/LOAD LSB
1 0 READ/LOAD MSB
1 1 READ/LOAD LSB FIRST, THEN MSB