Specifications

Operation Theorem •• 25
The operation sequences are:
1. Define the frequency (timer pacer rate)
2. The digital input data are saved in FIFO after a timer pacer pulse
is generated. The sampling is controlled by timer pacer.
3. The data saved in FIFO will be transferred to main memory of
your computer system directly and automatically. This is
controlled by bus mastering DMA control, this function is
supported by PCI controller chip.
The operation flow is show as below:
Timer 0
CLK0
GATE0
OUT0
8254 Timer/Counter
To Digital Input Trigger
Latch Digital Input
Digital Input FIFO
Bus mastering
DMA data Transfer
PC's Main Memory
1
2
3