Specifications

SI_T0: Status of timer 0 interrupt

1: OUT0 (output of timer 0) Interrupt occurred

0: No timer 0 Interrupt

SI_T1: Status of timer 1 interrupt

1: OUT1 (output of timer 1) Interrupt occurred

0: No timer 1 Interrupt

SI_T2: Status of timer 2 interrupt

1: OUT2 (output of timer 2) interrupt occurred

0: No timer 2 Interrupt

Note: All the interrupt status can be cleared by writing 1 to the

corresponding bit of the register. In order to make the interrupt

work properly, the interrupt service routine has to clear all the

interrupt status before end of the ISR.

♦♦ Timer Configuration Control:

The 8254 timer on the PCI-7200 can be configured as either

timer 0 cascaded with timer 2 or timer 1 cascaded with timer2.

These configuration are controlled by the following bits:

T0_T2: Timer 0 is cascaded with timer 2

1: Timer 0 and timer 2 are cascaded together, output of

timer 2 connects to the clock input of timer 0.

0: Not cascaded, the 4 MHz clock is connected to the

timer 0 clock input.

T1_T2: Timer 1 is cascaded with timer 2

1: Timer 1 and timer 2 are cascaded together, output of

timer 2 connects to the clock input of timer 1.

0: Not cascaded, the 4 MHz clock is connected to the

timer 1 clock input.