Specifications

20 •• Register Structure & Format
♦♦ Interrupt Control:
In PCI-7200, the interrupt can be triggered by many signal
sources such as O_ACK, I_REQ, timer 0, timer 1, and timer 2.
The interrupt source is controlled by the following bits:
IO_ACK: Interrupt is triggered by O_ACK signal.
1: O_ACK interrupt is enabled
0: O_ACK interrupt is disabled
II_REQ: Interrupt is triggered by I_REQ signal.
1: I_REQ interrupt is enabled
0: I_REQ interrupt is disabled
T0_EN: Interrupt is triggered by timer 0 output.
1: Timer 0 interrupt is enabled
0: Timer 0 interrupt is disabled
T1_EN: Interrupt is triggered by timer 1 output.
1: Timer 1 interrupt is enabled
0: Timer 1 interrupt is disabled
T2_EN: Interrupt is triggered by timer 2 output.
1: Timer 2 interrupt is enabled
0: Timer 2 interrupt is disabled
♦♦ Interrupt Status:
The following bits are used to check interrupt status:
SO_ACK: Status of O_ACK interrupt
1: O_ACK Interrupt occurred
0: No O_ACK interrupt
SI_REQ: Status of I_REQ interrupt
1: I_REQ Interrupt occurred
0: No I_REQ Interrupt